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1. 发明授权

US08921997B2 Electrical component and method of manufacturing the same 有权
标题翻译：电气元件及其制造方法
公开(公告)号：US08921997B2
公开(公告)日：2014-12-30
申请号：US13215457
申请日：2011-08-23
申请人： Yoshiaki Shimooka , Yoshiaki Sugizaki
发明人： Yoshiaki Shimooka , Yoshiaki Sugizaki
IPC分类号： H01L29/84 , H01L23/12 , B81C1/00 , H01L23/31
CPC分类号： B81C1/00333 , B81C2203/0136 , B81C2203/0145 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, an electrical component comprises a substrate, an element, a first layer, and a second layer. The element is formed on the substrate. The first layer forms a cavity accommodating the element on the substrate and includes through holes. The second layer is formed on the first layer and seals the through holes. The first layer includes the first film formed on the lower side and the second film which is formed on the first film and has a lower coefficient of thermal expansion than the first film.
摘要翻译：根据一个实施例，电气部件包括衬底，元件，第一层和第二层。元件形成在基板上。第一层形成容纳元件的空腔，并且包括通孔。第二层形成在第一层上并密封通孔。第一层包括在下侧形成的第一膜和形成在第一膜上的第二膜，并且具有比第一膜更低的热膨胀系数。

2. 发明申请

US20090263923A1 SEMICONDUCTOR DEVICE USING BURIED OXIDE LAYER AS OPTICAL WAVE GUIDES 有权
标题翻译：半导体器件使用铜氧化物层作为光波导
公开(公告)号：US20090263923A1
公开(公告)日：2009-10-22
申请号：US12496007
申请日：2009-07-01
申请人： Yoshiaki Shimooka
发明人： Yoshiaki Shimooka
IPC分类号： H01L33/00
CPC分类号： G02B6/4214
摘要： A semiconductor optical wave guide device is described in which a buried oxide layer (BOX) is capable of guiding light. Optical signals may be transmitted from one part of the semiconductor device to another, or with a point external to the semiconductor device, via the wave guide. In one example, an optical wave guide is provided including a core insulating layer encompassed by a clad insulating layer. The semiconductor device may contain an etched hole for guiding light to and from the core insulating layer from a transmitter or to a receiver.
摘要翻译：描述了一种半导体光波导装置，其中掩埋氧化物层（BOX）能够引导光。光信号可以经由波导从半导体器件的一部分传输到另一半导体器件或半导体器件外部。在一个示例中，提供了包括由包层绝缘层包围的芯绝缘层的光波导。半导体器件可以包含蚀刻孔，用于将光从发射器或接收器引导到芯绝缘层和从芯绝缘层引导光。

3. 发明申请

US20090188709A1 ELECTRICAL DEVICE 有权
标题翻译：电气设备
公开(公告)号：US20090188709A1
公开(公告)日：2009-07-30
申请号：US12358869
申请日：2009-01-23
申请人： Akihiro KOJIMA , Yoshiaki Sugizaki , Yoshiaki Shimooka
发明人： Akihiro KOJIMA , Yoshiaki Sugizaki , Yoshiaki Shimooka
IPC分类号： H05K1/16 , B05D5/12
CPC分类号： B81B7/0038 , B81B2201/0221 , B81B2203/04 , B81C1/00476
摘要： A substrate includes a functional element. An insulating first film forms a cavity which stores the functional element, together with the substrate, and includes a plurality of through-holes. An insulating second film covers the plurality of through-holes, is formed on the first film, and has a gas permeability which is higher than that of the first film. An insulating third film is formed on the second film and has a gas permeability which is lower than the second film. An insulating fourth film is formed on the third film and has an elasticity which is larger than the third film.
摘要翻译：衬底包括功能元件。绝缘的第一膜形成空腔，其与基板一起存储功能元件，并且包括多个通孔。绝缘的第二膜覆盖多个通孔，形成在第一膜上，并且具有比第一膜高的透气性。在第二薄膜上形成绝缘的第三薄膜，其透气度低于第二薄膜。绝缘的第四膜形成在第三膜上，并且具有大于第三膜的弹性。

4. 发明申请

US20070093052A1 SEMICONDUCTOR DEVICE HAVE MULTIPLE WIRING LAYERS AND METHOD OF PRODUCING THE SAME 失效
标题翻译：半导体器件具有多个布线层及其制造方法
公开(公告)号：US20070093052A1
公开(公告)日：2007-04-26
申请号：US11565530
申请日：2006-11-30
申请人： Yoshiaki Shimooka , Hideki Shibata , Hideshi Miyajima , Kazuhiro Tomioka
发明人： Yoshiaki Shimooka , Hideki Shibata , Hideshi Miyajima , Kazuhiro Tomioka
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76807 , H01L21/7682 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
摘要翻译：一种制造具有多个布线层的半导体器件的方法形成第一层间绝缘膜，在第一层间绝缘膜中形成用于布线的多个沟槽，在沟槽中填充金属膜以形成布线，蚀刻第一夹层将布线作为掩模，并且去除布线之间的层间绝缘膜以提供要填充的沟槽，并且在要填充的沟槽中填充由低介电常数材料制成的第二层间绝缘膜。

5. 发明授权

US08309858B2 Electrical device including a functional element in a cavity 有权
标题翻译：电气设备包括空腔中的功能元件
公开(公告)号：US08309858B2
公开(公告)日：2012-11-13
申请号：US12358869
申请日：2009-01-23
申请人： Akihiro Kojima , Yoshiaki Sugizaki , Yoshiaki Shimooka
发明人： Akihiro Kojima , Yoshiaki Sugizaki , Yoshiaki Shimooka
IPC分类号： H05K1/16
CPC分类号： B81B7/0038 , B81B2201/0221 , B81B2203/04 , B81C1/00476
摘要： A substrate includes a functional element. An insulating first film forms a cavity which stores the functional element, together with the substrate, and includes a plurality of through-holes. An insulating second film covers the plurality of through-holes, is formed on the first film, and has a gas permeability which is higher than that of the first film. An insulating third film is formed on the second film and has a gas permeability which is lower than the second film. An insulating fourth film is formed on the third film and has an elasticity which is larger than the third film.
摘要翻译：衬底包括功能元件。绝缘的第一膜形成空腔，其与基板一起存储功能元件，并且包括多个通孔。绝缘的第二膜覆盖多个通孔，形成在第一膜上，并且具有比第一膜高的透气性。在第二薄膜上形成绝缘的第三薄膜，其透气度低于第二薄膜。绝缘的第四膜形成在第三膜上，并且具有大于第三膜的弹性。

6. 发明授权

US07589014B2 Semiconductor device having multiple wiring layers and method of producing the same 失效
标题翻译：具有多个布线层的半导体器件及其制造方法
公开(公告)号：US07589014B2
公开(公告)日：2009-09-15
申请号：US11565530
申请日：2006-11-30
申请人： Yoshiaki Shimooka , Hideki Shibata , Hideshi Miyajima , Kazuhiro Tomioka
发明人： Yoshiaki Shimooka , Hideki Shibata , Hideshi Miyajima , Kazuhiro Tomioka
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76807 , H01L21/7682 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
摘要翻译：一种制造具有多个布线层的半导体器件的方法形成第一层间绝缘膜，在第一层间绝缘膜中形成用于布线的多个沟槽，在沟槽中填充金属膜以形成布线，蚀刻第一夹层将布线作为掩模，并且去除布线之间的层间绝缘膜以提供要填充的沟槽，并且在要填充的沟槽中填充由低介电常数材料制成的第二层间绝缘膜。

7. 发明申请

US20090146290A1 Interconnect Structure and Method for Semiconductor Device 有权
标题翻译：半导体器件的互连结构和方法
公开(公告)号：US20090146290A1
公开(公告)日：2009-06-11
申请号：US12368598
申请日：2009-02-10
申请人： Yoshiaki Shimooka , Tadashi Iijima
发明人： Yoshiaki Shimooka , Tadashi Iijima
IPC分类号： H01L23/12
CPC分类号： H01L21/76801 , H01L21/7688
摘要： An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.
摘要翻译：半导体器件中的互连方法可以包括检查层间电介质的各个区域以识别具有高密度或沟槽特征的浓度的区域的步骤。可以将绝缘体层添加到电介质中以有助于从电介质中除去吸收的杂质，但是可以从高密度区域移除，以允许较低密度区域增加除气。然后，由于沟槽特征，较低密度区域可以补偿在高密度区域上的增加的放气，并且可能导致整个器件在整个器件上具有更稳定的介电常数。

8. 发明申请

US20070246830A1 Long-lifetime interconnect structure and method for making 审中-公开
标题翻译：长寿命互联结构和制作方法
公开(公告)号：US20070246830A1
公开(公告)日：2007-10-25
申请号：US11408183
申请日：2006-04-21
申请人： Yoshiaki Shimooka
发明人： Yoshiaki Shimooka
IPC分类号： H01L23/52
CPC分类号： H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method for manufacturing are described wherein an insulating material adjacent to or at least partially surrounding a conductive interconnect has a coefficient of thermal expansion (CTE) equal to or larger than the CTE of the interconnect. For example, a copper-based damascene interconnect layer may be provided, wherein an inter-layer dielectric (ILD) a least partially surrounds the interconnect layer and a cap insulator is disposed on the interconnect layer. In such an embodiment, the CTE of the ILD and/or the cap insulator would be at least as large as the CTE of the interconnect layer. This may result in no stress or compressive stress being applied by the insulating material to the interconnect layer when the device has cooled, such as to room temperature, after formation of the various layers.
摘要翻译：描述了用于制造的互连结构和方法，其中与导电互连相邻或至少部分地围绕导电互连的绝缘材料具有等于或大于互连的CTE的热膨胀系数（CTE）。例如，可以提供铜基镶嵌互连层，其中层间电介质（ILD）至少部分地围绕互连层，并且帽绝缘体设置在互连层上。在这样的实施例中，ILD和/或帽绝缘体的CTE将至少与互连层的CTE一样大。当形成各层之后，当器件已经冷却到室温时，这可能导致绝缘材料施加到互连层的应力或压应力。

9. 发明授权

US06781236B2 Semiconductor device using a multilayer wiring structure 失效
标题翻译：使用多层布线结构的半导体器件
公开(公告)号：US06781236B2
公开(公告)日：2004-08-24
申请号：US10052259
申请日：2002-01-23
申请人： Yoshiaki Shimooka , Noriaki Matsunaga , Hideki Shibata
发明人： Yoshiaki Shimooka , Noriaki Matsunaga , Hideki Shibata
IPC分类号： H01L2312
CPC分类号： H01P3/088 , H01L23/5222 , H01L23/528 , H01L2223/6627 , H01L2223/6638 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011 , H01L2924/00
摘要： This invention includes a signal line 17, through which a signal having a desired frequency f0 passes, formed on a semiconductor substrate 10, and a differential signal line 13 through which a signal in opposite phase to the signal passing through the signal line passes, or which is connected to a ground power supply, the signal line and the differential signal line are formed so as to be substantially in parallel with each other via an insulating layer 15, and an actual wiring length l of the signal line is longer than a wiring length l0 determined by the following equation l 0 = L C + R 2 + 8 ⁢ π 2 ⁢ f 0 2 ⁢ L 2 4 ⁢ π 2 ⁢ f 0 2 ⁢ C 2 R 2 + 4 ⁢ π 2 ⁢ f 0 2 ⁢ L 2 where R represents a resistance component, L represents an inductance component, and C represents a capacitance component, per unit length of the signal line when no differential signal line exists.
摘要翻译：本发明包括形成在半导体衬底10上的具有期望频率f0的信号通过的信号线17和与通过信号线的信号相反相位的信号通过的差分信号线13，或连接到接地电源，信号线和差分信号线经由绝缘层15形成为基本上彼此平行，并且信号线的实际布线长度l比布线长长度l0由下式确定，其中R表示电阻分量，L表示电感分量，C表示当不存在差分信号线时信号线的每单位长度的电容分量。

10. 发明申请

US20130182366A1 MEMS DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： MEMS器件及其制造方法
公开(公告)号：US20130182366A1
公开(公告)日：2013-07-18
申请号：US13621982
申请日：2012-09-18
申请人： Kei Watanabe , Yoshiaki Shimooka , Tomohiro Saito , Tamio Ikehashi
发明人： Kei Watanabe , Yoshiaki Shimooka , Tomohiro Saito , Tamio Ikehashi
IPC分类号： H01G5/01
CPC分类号： H01G5/16 , H01G5/011 , Y10T29/42
摘要： According to one embodiment, a MEMS element comprises a first electrode fixed on a substrate, a second electrode formed above the first electrode to face it, and vertically movable, a first anchor portion formed on the substrate and configured to support the second electrode, and a first spring portion configured to connect the second electrode and the first anchor portion. The first spring portion includes a liner layer includes a brittle material in contact with the second electrode and the first anchor portion, and a base layer formed on the liner layer, includes a brittle material having a composition different from that of the liner layer, and having a film thickness larger than that of the liner layer.
摘要翻译：根据一个实施例，MEMS元件包括固定在基板上的第一电极，形成在第一电极上面以面对它并且可垂直移动的第二电极，形成在基板上并构造成支撑第二电极的第一锚定部分，以及构造成连接第二电极和第一锚固部分的第一弹簧部分。第一弹簧部分包括：衬垫层，包括与第二电极和第一锚定部分接触的脆性材料，以及形成在衬垫层上的基底层，包括具有不同于衬垫层的组成的脆性材料，以及其膜厚度大于衬层的膜厚。

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