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    • 1. 发明授权
      US07466594B2 Dynamic matching of signal path and reference path for sensing 有权
    • Dynamic matching of signal path and reference path for sensing
    • 信号路径和参考路径的动态匹配用于感测
    • US07466594B2
    • 2008-12-16
    • US11490539
    • 2006-07-19
    • Yair Sofer , Eduardo Maayan , Yoram Betser
    • Yair Sofer , Eduardo Maayan , Yoram Betser
    • G11C16/06
    • G11C16/28 , G11C7/14 , G11C16/0491
    • A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
    • 一种用于操作非易失性存储单元器件的方法，所述方法包括提供连接到字线和局部位线的存储器阵列单元的阵列，所述局部位线经由选择晶体管连接到全局位线，所述阵列被分成 隔离扇区，提供一个感测放大器，可操作以经由感测路径感测存储器阵列单元，该感测路径包括至少一个本地位线，至少一个选择晶体管，至少一个访问的全局位线和YMUX，提供 参考单元位于参考微型阵列中，参考单元连接到YMUX并且经由另一感测路径连接到读出放大器，利用公共位线（BL）驱动器驱动存储器阵列单元和参考单元 通过访问的全局位线经由YMUX连接到存储器阵列单元和参考单元，并且匹配存储器阵列单元的感测路径和参考cel的感测路径 通过在参考单元和读出放大器之间的感测路径中使用非访问的全局位线，将其传送到读出放大器。 可以动态地选择非访问的全局位线作为与用于驱动阵列的排水管和参考单元的全局位线相邻的全局位线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明申请
      US20060285408A1 METHOD CIRCUIT AND SYSTEM FOR COMPENSATING FOR TEMPERATURE INDUCED MARGIN LOSS IN NON-VOLATILE MEMORY CELLS 有权
    • METHOD CIRCUIT AND SYSTEM FOR COMPENSATING FOR TEMPERATURE INDUCED MARGIN LOSS IN NON-VOLATILE MEMORY CELLS
    • 用于补偿非挥发性记忆细胞中温度诱导的损伤的方法电路和系统
    • US20060285408A1
    • 2006-12-21
    • US11155252
    • 2005-06-17
    • Yoram Betser , Yair Sofer , Eduardo Maayan
    • Yoram Betser , Yair Sofer , Eduardo Maayan
    • G11C11/34
    • G11C16/3404 , G11C16/3445 , G11C16/3459
    • The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading. The pool of reference cells may consist of Program verify reference cells, or Erase verify reference cells.
    • 本发明包括用于在非易失性存储器（“NVM”）单元中随时间和超过工作温度范围补偿余量损失的方法和系统，该方法包括基于获得的温度读数来选择参考水平 从直接或间接热耦合到NVM单元的温度感测元件。 参考电平可以从由各种类型的参考电平组成的组中选择，或者可以通过基于温度读数调整单个参考的输出来获得，或者可以通过利用预先存储的转换 数据，该转换数据将给定的温度读数与相应的温度范围相关联，所述对应的温度范围又与相应的参考水平相关联。 可以提供同样参考单元的池，并且可以基于其与温度读数的关联从该池中选择参考水平。 参考单元池可以由程序验证参考单元或擦除验证参考单元组成。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US07184313B2 Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells 有权
    • Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
    • 用于补偿非易失性存储单元中温度引起的损耗的方法电路和系统
    • US07184313B2
    • 2007-02-27
    • US11155252
    • 2005-06-17
    • Yoram Betser , Yair Sofer , Eduardo Maayan
    • Yoram Betser , Yair Sofer , Eduardo Maayan
    • G11C16/04
    • G11C16/3404 , G11C16/3445 , G11C16/3459
    • The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled, directly or indirectly, to the NVM cell. The reference level may be selected from a group consisting of references levels of various types, or it may be obtained by adjusting the output of a single reference based on the temperature reading(s), or it may be obtained by utilizing pre-stored conversion data, which conversion data associates a given temperature reading with a corresponding temperature range that is, in turn, associated with a corresponding reference level. A pool of likewise reference cells may be provided, and the reference level may be selected from this pool, based on its association to the temperature reading. The pool of reference cells may consist of Program verify reference cells, or Erase verify reference cells.
    • 本发明包括用于在非易失性存储器（“NVM”）单元中随时间和超过工作温度范围补偿余量损失的方法和系统，该方法包括基于获得的温度读数来选择参考水平 从直接或间接热耦合到NVM单元的温度感测元件。 参考电平可以从由各种类型的参考电平组成的组中选择，或者可以通过基于温度读数调整单个参考的输出来获得，或者可以通过利用预先存储的转换 数据，该转换数据将给定的温度读数与相应的温度范围相关联，所述对应的温度范围又与相应的参考水平相关联。 可以提供同样参考单元的池，并且可以基于其与温度读数的关联从该池中选择参考水平。 参考单元池可以由程序验证参考单元或擦除验证参考单元组成。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20060034122A1 Dynamic matching of signal path and reference path for sensing 有权
    • Dynamic matching of signal path and reference path for sensing
    • US20060034122A1
    • 2006-02-16
    • US10916413
    • 2004-08-12
    • Yoram Betser , Eduardo Maayan , Yair Sofer
    • Yoram Betser , Eduardo Maayan , Yair Sofer
    • G11C16/06
    • G11C16/28 , G11C7/14 , G11C16/0491
    • A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明申请
      US20070171717A1 Dynamic matching of signal path and reference path for sensing 有权
    • Dynamic matching of signal path and reference path for sensing
    • 信号路径和参考路径的动态匹配用于感测
    • US20070171717A1
    • 2007-07-26
    • US11490539
    • 2006-07-19
    • Yair Sofer , Eduardo Maayan , Yoram Betser
    • Yair Sofer , Eduardo Maayan , Yoram Betser
    • G11C16/04 , G11C11/34 , G11C16/06
    • G11C16/28 , G11C7/14 , G11C16/0491
    • A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
    • 一种用于操作非易失性存储单元器件的方法，所述方法包括提供连接到字线和局部位线的存储器阵列单元的阵列，所述局部位线经由选择晶体管连接到全局位线，所述阵列被分成 隔离扇区，提供一个感测放大器，可操作以经由感测路径感测存储器阵列单元，该感测路径包括至少一个本地位线，至少一个选择晶体管，至少一个访问全局位线和YMUX，提供 参考单元位于参考微型阵列中，参考单元连接到YMUX并且经由另一感测路径连接到读出放大器，利用公共位线（BL）驱动器驱动存储器阵列单元和参考单元 通过访问的全局位线经由YMUX连接到存储器阵列单元和参考单元，并且匹配存储器阵列单元的感测路径和参考cel的感测路径 通过在参考单元和读出放大器之间的感测路径中使用非访问的全局位线，将其传送到读出放大器。 可以动态地选择非访问的全局位线作为与用于驱动阵列的排水管和参考单元的全局位线相邻的全局位线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07095655B2 Dynamic matching of signal path and reference path for sensing 有权
    • Dynamic matching of signal path and reference path for sensing
    • 信号路径和参考路径的动态匹配用于感测
    • US07095655B2
    • 2006-08-22
    • US10916413
    • 2004-08-12
    • Yoram Betser , Eduardo Maayan , Yair Sofer
    • Yoram Betser , Eduardo Maayan , Yair Sofer
    • G11C16/06
    • G11C16/28 , G11C7/14 , G11C16/0491
    • A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
    • 一种用于操作非易失性存储单元器件的方法，所述方法包括提供连接到字线和局部位线的存储器阵列单元的阵列，所述局部位线经由选择晶体管连接到全局位线，所述阵列被分成 隔离扇区，提供一个感测放大器，可操作以经由感测路径感测存储器阵列单元，该感测路径包括至少一个本地位线，至少一个选择晶体管，至少一个访问的全局位线和YMUX，提供 参考单元位于参考微型阵列中，参考单元连接到YMUX并且经由另一感测路径连接到读出放大器，利用公共位线（BL）驱动器驱动存储器阵列单元和参考单元 通过访问的全局位线经由YMUX连接到存储器阵列单元和参考单元，并且匹配存储器阵列单元的感测路径和参考cel的感测路径 通过在参考单元和读出放大器之间的感测路径中使用非访问的全局位线，将其传送到读出放大器。 可以动态地选择非访问的全局位线作为与用于驱动阵列的排水管和参考单元的全局位线相邻的全局位线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US07187595B2 Replenishment for internal voltage 有权
    • Replenishment for internal voltage
    • 补充内部电压
    • US07187595B2
    • 2007-03-06
    • US10862404
    • 2004-06-08
    • Yair Sofer , Ori Elyada , Yoram Betser
    • Yair Sofer , Ori Elyada , Yoram Betser
    • G11C5/14
    • G11C5/145 , G11C16/12
    • A replenish circuit for a semiconductor memory device, including a bias current generating unit adapted to generate a bias current, a frequency controllable oscillator adapted to receive the bias current and to provide an oscillating output, and a pulse generator adapted to receive the oscillating output and to generate first and second pulses as a function of the oscillating output, the second pulse being embedded in the first pulse, the first pulse causing the bias current generating unit to be connected to a power supply, and the second pulse being fed to sample-and-hold circuitry adapted to sample the bias current and hold the value thereof during the first pulse.
    • 一种用于半导体存储器件的补充电路，包括适于产生偏置电流的偏置电流产生单元，适于接收偏置电流并提供振荡输出的频率可控振荡器和适于接收振荡输出的脉冲发生器， 产生作为振荡输出的函数的第一和第二脉冲，第二脉冲被嵌入在第一脉冲中，第一脉冲使偏置电流产生单元连接到电源，并且第二脉冲被馈送到采样 - 并且保持电路适于在第一脉冲期间对偏置电流进行采样并保持其值。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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