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1. 发明授权

US07701235B2 Substrate test probing equipment having forcing part for test head and force-receiving pattern for probe card and methods of using the same 有权
标题翻译：具有强制部分用于探针卡的测试头和受力图案的基板测试探测设备及其使用方法
公开(公告)号：US07701235B2
公开(公告)日：2010-04-20
申请号：US12098778
申请日：2008-04-07
申请人： Chang-Hyun Cho , Joon-Yeon Kim , Sang-Gu Kang , Sung-Mo Kang , Sang-Kyu Yoo
发明人： Chang-Hyun Cho , Joon-Yeon Kim , Sang-Gu Kang , Sung-Mo Kang , Sang-Kyu Yoo
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R31/2891
摘要： Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.
摘要翻译：具有用于探针卡的力接收图案和用于测试头的强制部件的基板测试探测设备及其使用方法，其中用于探针卡的受力图案和用于测试头的强制部件当在高温和低温下测试半导体衬底时，可以抑制探针卡的热膨胀和收缩。为此，制备具有基板移动器，探针卡和测试头的基板测试探测设备，其中测试头具有强制部分，探针卡具有受力板。将半导体衬底放置在衬底移动器上以与探针卡电连接。半导体衬底由探针卡和测试头电测试。当半导体衬底被测试时，测试头的强制部分与探针卡的受力图案接触。

2. 发明授权

US06977528B2 Event driven dynamic logic for reducing power consumption 有权
标题翻译：事件驱动的动态逻辑，用于降低功耗
公开(公告)号：US06977528B2
公开(公告)日：2005-12-20
申请号：US10325594
申请日：2002-12-20
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： H03K3/012 , H03K19/00 , H03K19/096
CPC分类号： H03K3/012 , H03K19/0016 , H03K19/0963
摘要： Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.
摘要翻译：描述了方法和电路，用于当时钟信号不会在逻辑电路内产生期望的状态变化时，例如在输入，中间节点处，通过阻止时钟信号转换到逻辑电路来减少数字逻辑电路内的功耗，输出或组合。作为示例，如果要接收时钟信号转换，如果给定的一组逻辑输入不会导致状态的输出改变，则输入时钟被阻塞。作为进一步的示例，如果输入信号与输出信号匹配，则输入时钟在数据触发器中被阻塞，使得接收到时钟转换将不会在锁存输出中产生期望的状态变化。本发明可以用于创建较低功率的组合和/或顺序逻辑电路级，所述低功率组合和/或顺序的逻辑电路级经历栅极电容的不经济的充电和放电。

3. 发明授权

US06900690B2 Low-power high-performance integrated circuit and related methods 有权
公开(公告)号：US06900690B2
公开(公告)日：2005-05-31
申请号：US10729726
申请日：2003-12-05
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： H03K3/012 , H03K19/00 , G05F1/10
CPC分类号： H03K3/012 , H03K19/0016
摘要： An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

4. 发明授权

US06861911B2 Self-regulating voltage controlled oscillator 有权
标题翻译：自调节压控振荡器
公开(公告)号：US06861911B2
公开(公告)日：2005-03-01
申请号：US10357476
申请日：2003-02-04
申请人： In-Chul Hwang , Sung-Mo Kang , Bo-Eun Kim
发明人： In-Chul Hwang , Sung-Mo Kang , Bo-Eun Kim
IPC分类号： H03L7/099 , H03K3/011 , H03K3/03 , H03B27/00
CPC分类号： H03K3/011 , H03K3/0322
摘要： The present invention relates to the improvement of a phase noise characteristics of supply voltage in VCO. The delay in delay cells may be controlled to use the resistor of a transmission gate instead of a tail current. That is, the delay of cells is controlled by applying the overdrive voltage in transmission gate. And the self-regulating may be possible to composing a feedback inside the delay cells.
摘要翻译：本发明涉及VCO中电源电压的相位噪声特性的改进。可以控制延迟单元的延迟以使用传输门的电阻而不是尾电流。也就是说，通过在传输门中施加过驱动电压来控制电池的延迟。并且自调节可以在延迟单元内组成反馈。

5. 发明授权

US5468667A Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit 失效
标题翻译：将接地源放置在接地衬底MOS集成电路中的高效ESD / EOS保护方法
公开(公告)号：US5468667A
公开(公告)日：1995-11-21
申请号：US356768
申请日：1994-12-15
申请人： Carlos H. Diaz , Charvaka Duvvury , Sung-Mo Kang
发明人： Carlos H. Diaz , Charvaka Duvvury , Sung-Mo Kang
IPC分类号： H01L27/02 , H01L21/8234
CPC分类号： H01L27/0266
摘要： An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).
摘要翻译：一种用于保护集成电路的ESD / EOS保护电路（100）。 MOS晶体管（102）以具有多个漏极区（124），多个源极区（122）和多个栅极（118）的多指配置布置。第一金属层（162）基本上覆盖每个漏极区域（124），并且经由漏极触点（130）与每个漏极区域（124）接触。第二金属层（154）基本上覆盖每个源极区域（122），并且经由源极触点（128）与每个源极区域接触。多个源触点（128）位于与门（118）最小距离处。金属 - 金属触点（160）将第三金属层（156）与第二金属层（154）连接在每个源极区（122）上。

6. 发明授权

US07466191B2 Self reverse bias low-power high-performance storage circuitry and related methods 有权
标题翻译：自反向偏置低功耗高性能存储电路及相关方法
公开(公告)号：US07466191B2
公开(公告)日：2008-12-16
申请号：US11286197
申请日：2005-11-22
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： G11C5/14
CPC分类号： H03K3/3565 , G11C11/412 , G11C2207/2227 , H03K3/012 , H03K3/356156 , H03K19/0016
摘要： An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.
摘要翻译：提供一种集成电路，包括第一NMOS晶体管; 第一PMOS晶体管; 第二NMOS晶体管; 第二PMOS晶体管; 耦合到所述第一NMOS晶体管的第一源极/漏极的第一偏置电压节点; 耦合到所述第二PMOS的第一源极/漏极的第二偏置电压节点; 耦合到所述第一PMOS晶体管的栅极的第三偏置电压节点; 耦合到所述第二NMOS晶体管的栅极的第四偏置电压节点; 将所述第一NMOS晶体管的第二源极/漏极耦合到所述第一PMOS晶体管的第一源极/漏极的上拉节点; 将所述第二PMOS晶体管的第二源极/漏极耦合到所述第二NMOS晶体管的第一源极/漏极的下拉节点; 输入节点; 将所述第一PMOS晶体管的第二源极/漏极耦合到所述第二NMOS晶体管的第二源极/漏极的存储节点; 输出节点; 一个输入开关，其被耦合以可控地传送来自输入节点的输入数据值到第一NMOS晶体管的栅极和第二PMOS晶体管的栅极; 以及输出开关，其耦合以可控制地将存储的数据值从存储节点传送到输出节点。

7. 发明申请

US20060170437A1 Probe card for testing a plurality of semiconductor chips and method thereof 审中-公开
标题翻译：用于测试多个半导体芯片的探针卡及其方法
公开(公告)号：US20060170437A1
公开(公告)日：2006-08-03
申请号：US11330399
申请日：2006-01-12
申请人： Sang-Kyu Yoo , Ki-Sang Kang , Hoon-Jung Kim , Sung-Mo Kang , Chang-Hyun Cho
发明人： Sang-Kyu Yoo , Ki-Sang Kang , Hoon-Jung Kim , Sung-Mo Kang , Chang-Hyun Cho
IPC分类号： G01R31/02
CPC分类号： G01R1/07364 , G01R1/0491
摘要： A probe card for that may be used to test a plurality of semiconductor chips formed on a wafer. The probe card may include a substrate; a plurality of probe blocks that form a pattern corresponding to the pattern formed by the plurality of semiconductor chips formed on the wafer; and a plurality of probe needles formed in the probe blocks and arranged in a pattern corresponding to a plurality of pads formed in the plurality of semiconductor chips. The use of the probe card may decrease the testing time for the wafer.
摘要翻译：用于其的探针卡可用于测试形成在晶片上的多个半导体芯片。探针卡可以包括基底; 多个探针块，其形成与由形成在晶片上的多个半导体芯片形成的图案对应的图案; 以及形成在探针块中的多个探针，并以与形成在多个半导体芯片中的多个焊盘相对应的图案布置。探针卡的使用可能会降低晶片的测试时间。

8. 发明申请

US20060083052A1 Self reverse bias low-power high-performance storage circuitry and related methods 有权
标题翻译：自反向偏置低功耗高性能存储电路及相关方法
公开(公告)号：US20060083052A1
公开(公告)日：2006-04-20
申请号：US11286197
申请日：2005-11-22
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： G11C11/00
CPC分类号： H03K3/3565 , G11C11/412 , G11C2207/2227 , H03K3/012 , H03K3/356156 , H03K19/0016
摘要： An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.
摘要翻译：提供一种集成电路，包括第一NMOS晶体管; 第一PMOS晶体管; 第二NMOS晶体管; 第二PMOS晶体管; 耦合到所述第一NMOS晶体管的第一源极/漏极的第一偏置电压节点; 耦合到所述第二PMOS的第一源极/漏极的第二偏置电压节点; 耦合到所述第一PMOS晶体管的栅极的第三偏置电压节点; 耦合到所述第二NMOS晶体管的栅极的第四偏置电压节点; 将所述第一NMOS晶体管的第二源极/漏极耦合到所述第一PMOS晶体管的第一源极/漏极的上拉节点; 将所述第二PMOS晶体管的第二源极/漏极耦合到所述第二NMOS晶体管的第一源极/漏极的下拉节点; 输入节点; 将所述第一PMOS晶体管的第二源极/漏极耦合到所述第二NMOS晶体管的第二源极/漏极的存储节点; 输出节点; 一个输入开关，其被耦合以可控地传送来自输入节点的输入数据值到第一NMOS晶体管的栅极和第二PMOS晶体管的栅极; 以及输出开关，其耦合以可控制地将存储的数据值从存储节点传送到输出节点。

9. 发明授权

US06992915B2 Self reverse bias low-power high-performance storage circuitry and related methods 有权
公开(公告)号：US06992915B2
公开(公告)日：2006-01-31
申请号：US10402472
申请日：2003-03-27
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： H03K3/3565 , G11C11/412 , G11C2207/2227 , H03K3/012 , H03K3/356156 , H03K19/0016
摘要： An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.

10. 发明授权

US06888202B2 Low-power high-performance storage circuitry 有权
标题翻译：低功耗高性能存储电路
公开(公告)号：US06888202B2
公开(公告)日：2005-05-03
申请号：US10402059
申请日：2003-03-27
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： H03K3/012 , H03K3/356 , H03K3/3565 , H03K19/00 , H04L29/76
CPC分类号： H03K3/3565 , G11C11/412 , G11C2207/2227 , H03K3/012 , H03K3/356156 , H03K19/0016
摘要： An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate coupled to a first access control node; and a second low threshold voltage access transistor including a first S/D coupled to the second data node and to the gate of the first PMOS transistor and to the gate of the first NMOS transistor and including a second S/D coupled to a second data access node and including a gate coupled to a second access control node.
摘要翻译：提供一种集成电路，包括一个锁存电路，该锁存电路包括：第一反相器，包括第一高阈值电压PMOS晶体管和第一高阈值电压NMOS晶体管，第一数据节点包括第一PMOS的互连源/漏极（S / D） NMOS晶体管; 包括第二高阈值电压PMOS晶体管和第二高阈值电压NMOS晶体管的第二反相器，其中第二数据节点包括第二PMOS和NMOS晶体管的互连源/漏极（S / D）; 其中所述第一PMOS和所述第一NMOS晶体管的栅极耦合到所述第二数据节点; 其中所述第二PMOS晶体管和所述第二NMOS晶体管的栅极耦合到所述第一数据节点; 第一低阈值电压存取晶体管，包括耦合到第一数据节点和第二PMOS晶体管的栅极和第二NMOS晶体管的栅极的第一S / D并且包括耦合到第一数据存取的第二S / D 并且包括耦合到第一接入控制节点的门; 以及第二低阈值电压存取晶体管，其包括耦合到所述第二数据节点和所述第一PMOS晶体管的栅极和所述第一NMOS晶体管的栅极的第一S / D并且包括耦合到第二数据的第二S / D 接入节点并且包括耦合到第二接入控制节点的门。

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