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1. 发明申请

US20110001194A1 Hybrid Process for Forming Metal Gates 有权
标题翻译：用于形成金属门的混合工艺
公开(公告)号：US20110001194A1
公开(公告)日：2011-01-06
申请号：US12883241
申请日：2010-09-16
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , K. T. Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , K. T. Huang , Tze-Liang Lee
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

2. 发明申请

US20080173947A1 Hybrid process for forming metal gates 有权
标题翻译：用于形成金属门的混合工艺
公开(公告)号：US20080173947A1
公开(公告)日：2008-07-24
申请号：US11656711
申请日：2007-01-23
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , K. T. Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , K. T. Huang , Tze-Liang Lee
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

3. 发明授权

US08836038B2 CMOS dual metal gate semiconductor device 有权
标题翻译： CMOS双金属栅极半导体器件
公开(公告)号：US08836038B2
公开(公告)日：2014-09-16
申请号：US12883241
申请日：2010-09-16
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/28 , H01L29/66
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

4. 发明授权

US07812414B2 Hybrid process for forming metal gates 有权
标题翻译：用于形成金属门的混合工艺
公开(公告)号：US07812414B2
公开(公告)日：2010-10-12
申请号：US11656711
申请日：2007-01-23
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

5. 发明申请

US20080146012A1 NOVEL METHOD TO ADJUST WORK FUNCTION BY PLASMA ASSISTED METAL INCORPORATED DIELECTRIC 审中-公开
标题翻译：通过等离子体辅助金属合成电介质调整工作功能的新方法
公开(公告)号：US20080146012A1
公开(公告)日：2008-06-19
申请号：US11695227
申请日：2007-04-02
申请人： Wenli Lin , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee , Mong-Song Liang
发明人： Wenli Lin , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee , Mong-Song Liang
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/3115 , H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric on a substrate; introducing metal dopants into the gate dielectric; annealing the gate dielectric; and forming a gate electrode on the gate dielectric.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成栅极电介质; 将金属掺杂剂引入栅极电介质中; 退火栅电介质; 以及在栅极电介质上形成栅电极。

6. 发明授权

US09727049B2 Qualitative fault detection and classification system for tool condition monitoring and associated methods 有权
公开(公告)号：US09727049B2
公开(公告)日：2017-08-08
申请号：US13603079
申请日：2012-09-04
申请人： Chia-Tong Ho , Po-Feng Tsai , Jung-Chang Chen , Tze-Liang Lee , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
发明人： Chia-Tong Ho , Po-Feng Tsai , Jung-Chang Chen , Tze-Liang Lee , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
IPC分类号： G06F19/00 , G05B19/4065
CPC分类号： G05B19/4065 , G05B2219/37252 , G05B2219/45031
摘要： The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold.

7. 发明授权

US09612056B2 Wafer holder with varying surface property 有权
公开(公告)号：US09612056B2
公开(公告)日：2017-04-04
申请号：US13428749
申请日：2012-03-23
申请人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
发明人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
IPC分类号： F27D5/00 , F27B17/00 , H01L21/67 , H01L21/687
CPC分类号： H05B1/0233 , F27B17/0025 , F27D5/0037 , H01L21/306 , H01L21/477 , H01L21/67115 , H01L21/67303 , H01L21/683 , H01L21/68735 , H01L21/68757
摘要： An apparatus, a system and a method are disclosed. An exemplary apparatus includes a first portion configured to hold an overlying wafer. The first portion includes a central region and an edge region circumscribing the central region. The first portion further including an upper surface and a lower surface. The apparatus further includes a second portion extending beyond an outer radius of the wafer. The second portion including an upper surface and a lower surface. The lower surface of the first portion in the central region has a first reflective characteristic. The lower surface of the first portion in the edge region and the second portion have a second reflective characteristic.

8. 发明授权

US09054130B2 Bottle-neck recess in a semiconductor device 有权
标题翻译：半导体器件中的瓶颈凹槽
公开(公告)号：US09054130B2
公开(公告)日：2015-06-09
申请号：US12841763
申请日：2010-07-22
申请人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
发明人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
IPC分类号： H01L21/302 , H01L29/66 , H01L21/306 , H01L21/3065 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66636
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.
摘要翻译：本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域在硅衬底中，对硅衬底中的凹陷区域进行非偏置蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中生长半导体材料在硅衬底中。一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

9. 发明授权

US09011599B2 Method of temperature determination for deposition reactors 有权
标题翻译：沉积反应器温度测定方法
公开(公告)号：US09011599B2
公开(公告)日：2015-04-21
申请号：US12835789
申请日：2010-07-14
申请人： Jhi-Cherng Lu , Jr-Hung Li , Chii-Horng Li , Pang-Yen Tsai , Bing-Hung Chen , Tze-Liang Lee
发明人： Jhi-Cherng Lu , Jr-Hung Li , Chii-Horng Li , Pang-Yen Tsai , Bing-Hung Chen , Tze-Liang Lee
IPC分类号： C30B25/08 , C30B25/16 , C30B29/06 , C30B29/08 , C30B29/52 , H01L21/02 , H01L21/66
CPC分类号： C30B25/16 , C30B29/06 , C30B29/08 , C30B29/52 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L22/10 , H01L22/12 , Y10T117/1004 , Y10T117/1008
摘要： A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.
摘要翻译：确定沉积反应器中的温度的方法包括以下步骤：将硅锗的第一外延层沉积在衬底上，在第一外延层上沉积硅的第二外延层，测量第二外延层的厚度并确定使用测量的第二外延层的厚度在沉积反应器中进行温度测量。该方法还可以包括使用加热装置和温度测量装置将沉积反应器加热至约预定温度，并产生指示沉积反应器内的温度的信号。该方法还可以包括以下步骤：将测量的厚度与对应于预定温度的第二外延层的预定厚度进行比较，并使用第二外延层的测量厚度和第二外延层的预定厚度来确定沉积反应器中的温度外延层。

10. 发明授权

US08889501B2 Methods for forming MOS devices with raised source/drain regions 有权
标题翻译：用于形成具有升高的源极/漏极区域的MOS器件的方法
公开(公告)号：US08889501B2
公开(公告)日：2014-11-18
申请号：US13486240
申请日：2012-06-01
申请人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young , Yen-Ru Lee , Chii-Horng Li , Tze-Liang Lee
发明人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young , Yen-Ru Lee , Chii-Horng Li , Tze-Liang Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/11
CPC分类号： H01L27/1116 , H01L21/823807 , H01L21/823814
摘要： A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.
摘要翻译：一种方法包括在半导体衬底上形成第一器件的第一栅极堆叠，以及在半导体衬底上形成第二MOS器件的第二栅极堆叠。执行第一外延以形成用于第二MOS器件的源/漏应力源，其中源极/漏极应力器与第二栅极堆叠相邻。执行第二外延以同时形成第一硅层和第二硅层，其中第一硅层位于半导体衬底的第一部分之上并且与第一栅极堆叠相邻。第二硅层与源极/漏极应力源重叠。

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