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1. 发明授权

US09612056B2 Wafer holder with varying surface property 有权
公开(公告)号：US09612056B2
公开(公告)日：2017-04-04
申请号：US13428749
申请日：2012-03-23
申请人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
发明人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
IPC分类号： F27D5/00 , F27B17/00 , H01L21/67 , H01L21/687
CPC分类号： H05B1/0233 , F27B17/0025 , F27D5/0037 , H01L21/306 , H01L21/477 , H01L21/67115 , H01L21/67303 , H01L21/683 , H01L21/68735 , H01L21/68757
摘要： An apparatus, a system and a method are disclosed. An exemplary apparatus includes a first portion configured to hold an overlying wafer. The first portion includes a central region and an edge region circumscribing the central region. The first portion further including an upper surface and a lower surface. The apparatus further includes a second portion extending beyond an outer radius of the wafer. The second portion including an upper surface and a lower surface. The lower surface of the first portion in the central region has a first reflective characteristic. The lower surface of the first portion in the edge region and the second portion have a second reflective characteristic.

2. 发明申请

US20130252189A1 Wafer Holder With Varying Surface Property 有权
标题翻译：晶圆座具有不同的表面特性
公开(公告)号：US20130252189A1
公开(公告)日：2013-09-26
申请号：US13428749
申请日：2012-03-23
申请人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
发明人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
IPC分类号： F27D1/00 , F27D5/00
CPC分类号： H05B1/0233 , F27B17/0025 , F27D5/0037 , H01L21/306 , H01L21/477 , H01L21/67115 , H01L21/67303 , H01L21/683 , H01L21/68735 , H01L21/68757
摘要： An apparatus, a system and a method are disclosed. An exemplary apparatus includes a first portion configured to hold an overlying wafer. The first portion includes a central region and an edge region circumscribing the central region. The first portion further including an upper surface and a lower surface. The apparatus further includes a second portion extending beyond an outer radius of the wafer. The second portion including an upper surface and a lower surface. The lower surface of the first portion in the central region has a first reflective characteristic. The lower surface of the first portion in the edge region and the second portion have a second reflective characteristic.
摘要翻译：公开了一种装置，系统和方法。示例性装置包括被配置为保持覆盖晶片的第一部分。第一部分包括中心区域和围绕中心区域的边缘区域。第一部分还包括上表面和下表面。该装置还包括延伸超过晶片的外半径的第二部分。第二部分包括上表面和下表面。中心区域的第一部分的下表面具有第一反射特性。边缘区域中的第一部分的下表面和第二部分具有第二反射特性。

3. 发明申请

US20130252424A1 WAFER HOLDER WITH TAPERED REGION 有权
标题翻译：带有尖端区域的波形支架
公开(公告)号：US20130252424A1
公开(公告)日：2013-09-26
申请号：US13426334
申请日：2012-03-21
申请人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
发明人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
IPC分类号： H01L21/306 , H01L21/324 , H01L21/302 , H01L21/683 , H01L21/477
CPC分类号： H05B1/0233 , F27B17/0025 , F27D5/0037 , H01L21/306 , H01L21/477 , H01L21/67115 , H01L21/67303 , H01L21/683 , H01L21/68735 , H01L21/68757
摘要： An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness.
摘要翻译：公开了一种装置，系统和方法。示例性装置包括具有第一部分和第二部分的晶片保持器。第一和第二部分由相同的连续材料形成。第一部分包括第一上表面和第一下表面，第二部分包括第二上表面和第二下表面。该装置还包括第一和第二部分之间的界面。界面提供了使得第一部分的第一上表面趋向于第二部分的第二上表面的过渡。该装置还包括形成在第一部分中的锥形区域。锥形区域从距离晶片保持器的中心线的径向距离开始，并且在界面处终止。锥形区域具有逐渐减小到最终厚度的初始厚度。

4. 发明授权

US09099514B2 Wafer holder with tapered region 有权
标题翻译：晶圆座具有锥形区域
公开(公告)号：US09099514B2
公开(公告)日：2015-08-04
申请号：US13426334
申请日：2012-03-21
申请人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
发明人： Yi-Hung Lin , Li-Ting Wang , Tze-Liang Lee
IPC分类号： A47G19/08 , H01L21/687 , H01L21/683 , H01L21/477 , H01L21/306 , H01L21/673
CPC分类号： H05B1/0233 , F27B17/0025 , F27D5/0037 , H01L21/306 , H01L21/477 , H01L21/67115 , H01L21/67303 , H01L21/683 , H01L21/68735 , H01L21/68757
摘要： An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness.
摘要翻译：公开了一种装置，系统和方法。示例性装置包括具有第一部分和第二部分的晶片保持器。第一和第二部分由相同的连续材料形成。第一部分包括第一上表面和第一下表面，第二部分包括第二上表面和第二下表面。该装置还包括第一和第二部分之间的界面。界面提供了使得第一部分的第一上表面趋向于第二部分的第二上表面的过渡。该装置还包括形成在第一部分中的锥形区域。锥形区域从距离晶片保持器的中心线的径向距离开始，并且在界面处终止。锥形区域具有逐渐减小到最终厚度的初始厚度。

5. 发明申请

US20110287611A1 Reducing Variation by Using Combination Epitaxy Growth 有权
标题翻译：通过组合外延生长减少变异
公开(公告)号：US20110287611A1
公开(公告)日：2011-11-24
申请号：US13030850
申请日：2011-02-18
申请人： Yu-Hung Cheng , Chii-Horng Li , Tze-Liang Lee , Yi-Hung Lin
发明人： Yu-Hung Cheng , Chii-Horng Li , Tze-Liang Lee , Yi-Hung Lin
IPC分类号： H01L21/20
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02636 , H01L21/02639 , H01L29/0847 , H01L29/7848
摘要： A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.
摘要翻译：一种用于形成半导体结构的方法包括在晶片上的半导体衬底上形成栅叠层; 在所述半导体衬底中形成凹槽并邻近所述栅叠层; 以及进行选择性外延生长以在所述凹部中生长半导体材料以形成外延区域。执行选择性外延生长的步骤包括以第一生长阶段中使用的工艺气体的第一生长蚀刻（E / G）比率进行第一生长阶段; 以及在与第一E / G比不同的第二生长阶段中使用的处理气体的第二E / G比进行第二生长阶段。

6. 发明授权

US09647066B2 Dummy FinFET structure and method of making same 有权
公开(公告)号：US09647066B2
公开(公告)日：2017-05-09
申请号：US13454960
申请日：2012-04-24
申请人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
发明人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
IPC分类号： H01L27/088 , H01L29/10 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/20
CPC分类号： H01L29/10 , H01L21/823431 , H01L27/0886 , H01L29/6681 , H01L29/785
摘要： A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.

7. 发明授权

US08835267B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08835267B2
公开(公告)日：2014-09-16
申请号：US13248319
申请日：2011-09-29
申请人： Yen-Ru Lee , Ming-Hua Yu , Tze-Liang Lee , Chii-Horng Li , Pang-Yen Tsai , Lilly Su , Yi-Hung Lin , Yu-Hung Cheng
发明人： Yen-Ru Lee , Ming-Hua Yu , Tze-Liang Lee , Chii-Horng Li , Pang-Yen Tsai , Lilly Su , Yi-Hung Lin , Yu-Hung Cheng
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7846
摘要： A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of a substrate to enhance carrier mobility and upgrade the device performance. In an embodiment, the improved formation method is achieved using an etching process to redistribute the strained material by removing at least a portion of the corner to be located in the cavity.
摘要翻译：公开了一种制造半导体器件的方法。应变材料形成在衬底的空腔中并与衬底中的隔离结构相邻。应变材料在基底表面上方有一角。所公开的方法提供了一种用于形成邻近隔离结构的应变材料的改进方法，其中衬底的腔中具有增加的部分，以增强载体移动性并提高器件性能。在一个实施例中，改进的形成方法是通过使用蚀刻工艺来实现的，该蚀刻工艺通过去除位于空腔中的角部的至少一部分来重新分布应变材料。

8. 发明申请

US20080160709A1 Advanced activation approach for MOS devices 有权
标题翻译： MOS器件的高级激活方法
公开(公告)号：US20080160709A1
公开(公告)日：2008-07-03
申请号：US11648371
申请日：2006-12-29
申请人： Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Keh-Chiang Ku , Chun-Feng Nieh , Li-Ting Wang , Hsun Chang
发明人： Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Keh-Chiang Ku , Chun-Feng Nieh , Li-Ting Wang , Hsun Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/324 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成邻近所述栅极电介质和所述栅电极的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

9. 发明申请

US20070284615A1 Ultra-shallow and highly activated source/drain extension formation using phosphorus 有权
标题翻译：使用磷的超浅和高活化的源/漏延伸形成
公开(公告)号：US20070284615A1
公开(公告)日：2007-12-13
申请号：US11521660
申请日：2006-09-15
申请人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
发明人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/739
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/0847 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.
摘要翻译：半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

10. 发明申请

US20130277760A1 Dummy FinFET Structure and Method of Making Same 有权
标题翻译：虚拟FinFET结构及其制作方法
公开(公告)号：US20130277760A1
公开(公告)日：2013-10-24
申请号：US13454960
申请日：2012-04-24
申请人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
发明人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
IPC分类号： H01L27/088 , H01L21/20
CPC分类号： H01L29/10 , H01L21/823431 , H01L27/0886 , H01L29/6681 , H01L29/785
摘要： A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.
摘要翻译： FinFET器件可以包括横向邻近有源FinFET结构的虚设FinFET结构，以减少应力不平衡以及应力不平衡对有源FinFET结构的影响。 FinFET器件包括包括多个半导体鳍片的有源FinFET和包括多个半导体鳍片的虚设FinFET。有源FinFET和虚拟FinFET彼此横向间隔开与有源FinFET的鳍间距有关的间隔。

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