专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08320212B2 Voltage stabilization circuit and semiconductor memory apparatus using the same 失效
标题翻译：稳压电路及使用其的半导体存储装置
公开(公告)号：US08320212B2
公开(公告)日：2012-11-27
申请号：US13155901
申请日：2011-06-08
申请人： Yong-Mi Kim , Jeong-Tae Hwang , Jeong-Hun Lee
发明人： Yong-Mi Kim , Jeong-Tae Hwang , Jeong-Hun Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/02 , G11C7/22 , G11C7/222
摘要： A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.
摘要翻译：半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线响应于检测信号。

2. 发明申请

US20100290304A1 VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME 失效
标题翻译：使用电压稳定电路和半导体存储器件
公开(公告)号：US20100290304A1
公开(公告)日：2010-11-18
申请号：US12494815
申请日：2009-06-30
申请人： Jeong-Hun Lee , Yong-Mi Kim , Jeong-Tae Hwang
发明人： Jeong-Hun Lee , Yong-Mi Kim , Jeong-Tae Hwang
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/02 , G11C7/22 , G11C7/222
摘要： A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.
摘要翻译：半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线响应于检测信号。

3. 发明授权

US08503260B2 Semiconductor memory device, method of testing the same and system of testing the same 有权
标题翻译：半导体存储器件，测试方法与测试系统相同
公开(公告)号：US08503260B2
公开(公告)日：2013-08-06
申请号：US13104262
申请日：2011-05-10
申请人： Jeong-Tae Hwang , Jeong-Hun Lee
发明人： Jeong-Tae Hwang , Jeong-Hun Lee
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/28
摘要： A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.
摘要翻译：一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。

4. 发明授权

US08386858B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08386858B2
公开(公告)日：2013-02-26
申请号：US12616529
申请日：2009-11-11
申请人： Jeong-Hun Lee , Jeong-Tae Hwang
发明人： Jeong-Hun Lee , Jeong-Tae Hwang
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/46
摘要： A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.
摘要翻译：半导体存储器件能够在其各种操作模式下执行测试操作。特别地，半导体存储器件可以进入其他模式的测试模式以及全部银行预充电模式。半导体存储器件包括：测试模式控制块，被配置为在激活模式下产生预定间隔使能的测试信号;以及模式寄存器组控制模块，被配置为使得模式寄存器设置信号能够在预定间隔内进行测试操作响应测试信号。

5. 发明申请

US20120155203A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND SYSTEM OF TESTING THE SAME 有权
标题翻译：半导体存储器件，其测试方法和测试相同的系统
公开(公告)号：US20120155203A1
公开(公告)日：2012-06-21
申请号：US13104262
申请日：2011-05-10
申请人： Jeong-Tae Hwang , Jeong-Hun Lee
发明人： Jeong-Tae Hwang , Jeong-Hun Lee
IPC分类号： G11C29/18
CPC分类号： G11C29/28
摘要： A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.
摘要翻译：一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。

6. 发明申请

US20110004794A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110004794A1
公开(公告)日：2011-01-06
申请号：US12616529
申请日：2009-11-11
申请人： Jeong-Hun Lee , Jeong-Tae Hwang
发明人： Jeong-Hun Lee , Jeong-Tae Hwang
IPC分类号： G11C29/10 , G06F11/263
CPC分类号： G11C29/46
摘要： A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.
摘要翻译：半导体存储器件能够在其各种操作模式下执行测试操作。特别地，半导体存储器件可以进入其他模式的测试模式以及全部银行预充电模式。半导体存储器件包括：测试模式控制块，被配置为在激活模式下产生预定间隔使能的测试信号;以及模式寄存器组控制模块，被配置为使得模式寄存器设置信号能够在预定间隔内进行测试操作响应测试信号。

7. 发明授权

US07983106B2 Voltage stabilization circuit and semiconductor memory apparatus using the same 失效
标题翻译：稳压电路及使用其的半导体存储装置
公开(公告)号：US07983106B2
公开(公告)日：2011-07-19
申请号：US12494815
申请日：2009-06-30
申请人： Yong-Mi Kim , Jeong-Tea Hwang , Jeong-Hun Lee
发明人： Yong-Mi Kim , Jeong-Tea Hwang , Jeong-Hun Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/02 , G11C7/22 , G11C7/222
摘要： A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.
摘要翻译：半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线响应于检测信号。

8. 发明授权

US08151149B2 Semiconductor memory apparatus and method of testing the same 失效
标题翻译：半导体存储器及其测试方法
公开(公告)号：US08151149B2
公开(公告)日：2012-04-03
申请号：US12649743
申请日：2009-12-30
申请人： Jeong-Hun Lee , Yong-Mi Kim , Jeong-Tea Hwang
发明人： Jeong-Hun Lee , Yong-Mi Kim , Jeong-Tea Hwang
IPC分类号： G11C29/00
CPC分类号： G11C29/46
摘要： A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.
摘要翻译：根据实施例的半导体存储装置包括测试模式控制器，第一数据对准单元，解码器，测试执行单元和第二数据对准单元。测试模式控制器被配置为响应于测试模式设置信号和读取命令而产生测试使能信号。第一数据对准单元被配置为并行地对准串联输入的第一输入数据，产生第一对准数据，并将其发送到第一数据驱动器。解码器被配置为响应于测试使能信号解码第一对准数据并产生解码信号。测试执行单元被配置为响应于解码信号执行预设测试模式。第二数据对准单元被配置为响应于测试使能信号并行输入串联的第二输入数据，产生第二对准数据并将其发送到第二数据驱动器。

9. 发明授权

US07689425B2 Quality of service call routing system using counselor and speech recognition engine and method thereof 有权
标题翻译：使用顾问和语音识别引擎的服务质量呼叫路由系统及其方法
公开(公告)号：US07689425B2
公开(公告)日：2010-03-30
申请号：US11153660
申请日：2005-06-15
申请人： Do-Sung Kim , Dong-Soon Min , Kwan-Sik Yoo , Seung-Woo Chung , Jeong-Hun Lee
发明人： Do-Sung Kim , Dong-Soon Min , Kwan-Sik Yoo , Seung-Woo Chung , Jeong-Hun Lee
IPC分类号： G10L21/00
CPC分类号： G10L15/22 , H04M3/5166 , H04M2203/2011
摘要： A QoS call routing system using a counselor and a speech recognition engine comprises a speech recognition engine for recognizing speech and outputting characters and speech recognition results; a first counselor group terminal for reproducing the client's speech file to a counselor of a first counselor group so that the counselor may recognize the speech when the speech recognition result by the speech recognition engine is less than a reference value; a second counselor group terminal for allowing a counselor of a second counselor group to hear the client's speech so that the counselor may recognize the speech when the recognition by the counselor of the first counselor group has failed; and an IVR server for controlling the engine and terminals to provide information to the client.
摘要翻译：使用顾问和语音识别引擎的QoS呼叫路由系统包括用于识别语音并输出字符和语音识别结果的语音识别引擎; 第一顾问组终端，用于将顾客的语音文件再现给第一顾问组的顾问，使得当语音识别引擎的语音识别结果小于参考值时，辅导员可以识别语音; 第二辅导组织终端，允许第二顾问组的顾问听取客户的演讲，以便辅导员在第一顾问组的顾问的认可失败时可以承认该演讲; 以及用于控制引擎和终端以向客户端提供信息的IVR服务器。

10. 发明授权

US06833522B1 Key switch device and method for manufacturing the same 失效
标题翻译：钥匙开关装置及其制造方法
公开(公告)号：US06833522B1
公开(公告)日：2004-12-21
申请号：US10781996
申请日：2004-02-19
申请人： Kyung-Su Park , Chul-Gi Min , Jeong-Hun Lee
发明人： Kyung-Su Park , Chul-Gi Min , Jeong-Hun Lee
IPC分类号： H01H1370
CPC分类号： H01H3/125 , H01H2215/004
摘要： A key switch device includes inner and outer link members connected to each other to mutually move in a scissors fashion, a key top having receiving portions for receiving the support protrusions provided at respective upper ends of the link members, a hollow elastic switch provided at an inner surface thereof with a downward protrusion for performing a switching operation in accordance with vertical movement of the key top, a support plate arranged beneath the key top, a membrane arranged on the support plate, and a mounting member arranged on the membrane, a central opening for receiving the elastic switch, and fitting holes allowing the cocking members to be fitted therein.
摘要翻译：钥匙开关装置包括彼此连接的内部和外部连杆构件以剪刀的方式相互移动，键顶部具有用于接收设置在连杆构件的相应上端处的支撑突起的接收部分，其内表面具有向下突起，用于根据键顶的垂直运动执行切换操作，安装在键顶下方的支撑板，布置在支撑板上的膜和布置在膜上的安装构件，中心用于接收弹性开关的开口，以及允许将推动构件安装在其中的装配孔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式