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1. 发明授权

US08704561B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US08704561B2
公开(公告)日：2014-04-22
申请号：US13285088
申请日：2011-10-31
申请人： Hye-Young Lee , Yong-Mi Kim
发明人： Hye-Young Lee , Yong-Mi Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812
摘要： A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.
摘要翻译：延迟锁定环包括延迟调整单元，其被配置为延迟第一时钟信号输出与第一时钟信号锁相的第二时钟信号，并响应于第一时钟信号和第二时钟信号产生延迟控制信号，并且可变延迟线，被配置为通过响应于延迟控制信号延迟第一时钟信号来输出第三时钟信号。

2. 发明授权

US08680841B2 Reference voltage generation circuitary for semiconductor apparatus and method for checking a reference voltage 有权
标题翻译：用于半导体装置的参考电压产生电路和用于检查参考电压的方法
公开(公告)号：US08680841B2
公开(公告)日：2014-03-25
申请号：US12983090
申请日：2010-12-31
申请人： Jeong Hun Lee , Yong Mi Kim , Jeong Tae Hwang
发明人： Jeong Hun Lee , Yong Mi Kim , Jeong Tae Hwang
IPC分类号： G05F1/607 , G05F1/614
CPC分类号： G11C5/147 , G11C29/021
摘要： A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.
摘要翻译：一种半导体装置，包括：被配置为生成多个不同的比较电压的比较电压生成单元，被配置为从外部系统接收生成代码的基准电压生成单元，根据生成代码选择所述多个不同的比较电压中的一个并产生参考电压，参考电压确定单元被配置为从外部系统接收生成代码和预期参考电压，检查预期参考电压的电平是否在目标范围内，并将检查结果输出到外部系统。

3. 发明申请

US20130038363A1 DELAY LOCKED LOOP 有权
标题翻译：延迟锁定环
公开(公告)号：US20130038363A1
公开(公告)日：2013-02-14
申请号：US13285088
申请日：2011-10-31
申请人： Hye-Young LEE , Yong-Mi Kim
发明人： Hye-Young LEE , Yong-Mi Kim
IPC分类号： H03L7/08
CPC分类号： H03L7/0805 , H03L7/0812
摘要： A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.
摘要翻译：延迟锁定环包括延迟调整单元，其被配置为延迟第一时钟信号输出与第一时钟信号锁相的第二时钟信号，并响应于第一时钟信号和第二时钟信号产生延迟控制信号，并且可变延迟线，被配置为通过响应于延迟控制信号延迟第一时钟信号来输出第三时钟信号。

4. 发明申请

US20120044780A1 DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器的数据输出电路
公开(公告)号：US20120044780A1
公开(公告)日：2012-02-23
申请号：US12983185
申请日：2010-12-31
申请人： Yong Mi KIM , Jeong Hun LEE
发明人： Yong Mi KIM , Jeong Hun LEE
IPC分类号： G11C8/18
CPC分类号： G11C7/1057 , G11C7/1066 , G11C8/18
摘要： A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data.
摘要翻译：半导体存储装置的数据输出电路包括：数据控制驱动器，被配置为驱动上升数据和下降数据以输出控制上升数据并控制下降数据或驱动电平数据以输出控制上升数据和控制下降数据到输出电平测试信号; DLL时钟控制单元，被配置为响应于使能信号和输出电平测试信号驱动上升时钟和下降时钟以输出控制上升时钟和控制下降时钟; 以及时钟同步单元，被配置为使控制上升数据和控制下降数据与控制上升时钟和控制下降时钟同步，以输出串行上升数据和串行下降数据。

5. 发明授权

US07983106B2 Voltage stabilization circuit and semiconductor memory apparatus using the same 失效
标题翻译：稳压电路及使用其的半导体存储装置
公开(公告)号：US07983106B2
公开(公告)日：2011-07-19
申请号：US12494815
申请日：2009-06-30
申请人： Yong-Mi Kim , Jeong-Tea Hwang , Jeong-Hun Lee
发明人： Yong-Mi Kim , Jeong-Tea Hwang , Jeong-Hun Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/02 , G11C7/22 , G11C7/222
摘要： A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.
摘要翻译：半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线响应于检测信号。

6. 发明授权

US07489585B2 Global signal driver for individually adjusting driving strength of each memory bank 失效
标题翻译：用于单独调整每个存储体的驱动强度的全局信号驱动器
公开(公告)号：US07489585B2
公开(公告)日：2009-02-10
申请号：US11478117
申请日：2006-06-30
申请人： Sung-Joo Ha , Yong-Mi Kim
发明人： Sung-Joo Ha , Yong-Mi Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1048 , G11C11/4096 , G11C2207/2254
摘要： A global signal driving device includes a driving control unit for generating a plurality of driving control signals differently configured according to transmission distances of a global signal to a plurality of banks by decoding a bank address; and a driving unit for adjusting a driving strength for driving the global signal based on the plurality of driving control signals in order to drive the global signal to the plurality of banks.
摘要翻译：全局信号驱动装置包括：驱动控制单元，用于通过解码存储体地址来产生根据全局信号到多个存储体的传输距离不同地配置的多个驱动控制信号; 以及驱动单元，用于基于所述多个驱动控制信号来调整用于驱动全局信号的驱动强度，以便将全局信号驱动到多个存储体。

7. 发明申请

US20070002988A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070002988A1
公开(公告)日：2007-01-04
申请号：US11321454
申请日：2005-12-30
申请人： Yong-Mi Kim
发明人： Yong-Mi Kim
IPC分类号： H04L7/00
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A semiconductor memory device according to the present invention can change adjusting timing of ODT operation in convenience and have an optimized ODT timing whether the semiconductor memory device is putted on ether rank of a module. The present invention includes an impedance adjusting unit for adjusting an impedance value of an input pad in response to an impedance selecting signal; an ODT operating control unit for controlling the impedance adjusting unit as generating the impedance selection signal using an decoding signal and an ODT timing signal; a delay adjusting unit for delaying an internal control clock for a predetermined timing to thereby generate the ODT timing signal; and an ODT timing control unit for controlling the delay adjusting unit to decide the value of the predetermined timing according to whether or not the semiconductor memory device is arranged to a first rank or a second rank in a module.
摘要翻译：根据本发明的半导体存储器件可以方便地改变ODT操作的调整定时，并且具有优化的ODT时序，无论半导体存储器件是否被放置在模块的以太等级。本发明包括：阻抗调整单元，用于响应于阻抗选择信号调整输入焊盘的阻抗值; ODT操作控制单元，用于使用解码信号和ODT定时信号来控制阻抗调节单元生成阻抗选择信号; 延迟调整单元，用于将内部控制时钟延迟预定定时，从而产生ODT定时信号; 以及ODT定时控制单元，用于根据半导体存储器件是否被布置成模块中的第一等级或第二等级，来控制延迟调整单元来确定预定定时的值。

8. 发明申请

US20060255830A1 On-die termination apparatus 失效
标题翻译：片上终端设备
公开(公告)号：US20060255830A1
公开(公告)日：2006-11-16
申请号：US11478084
申请日：2006-06-30
申请人： Yong-Mi Kim
发明人： Yong-Mi Kim
IPC分类号： H03K19/003
CPC分类号： H04L25/0298 , G11C7/1048 , G11C7/1066 , G11C29/02 , G11C29/025 , G11C29/50008
摘要： An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding unit for decoding an inputted address to output a plurality of decoding signals to set a termination impedance; an ODT control unit for selectively activating a plurality of pull-up control signals and a multiplicity of pull-down control signals by logically combining the plurality of decoding signals, pull-up test signals and pull-down test signals; and an ODT unit including a plurality of main termination units to test the termination impedance by separately activating the plurality of main termination units based on the plurality of pull-up control signals and the multiplicity of pull-down control signals.
摘要翻译：片上端接装置通过单独控制设置在主片上端接块中的上拉晶体管和下拉晶体管来保证期望的规格裕度。片上终端电路包括扩展模式寄存器组解码单元，用于解码输入的地址以输出多个解码信号以设置终端阻抗; ODT控制单元，用于通过逻辑组合多个解码信号，上拉测试信号和下拉测试信号来选择性地激活多个上拉控制信号和多个下拉控制信号; 以及ODT单元，其包括多个主终端单元，用于基于所述多个上拉控制信号和多个下拉控制信号单独激活所述多个主终端单元来测试终端阻抗。

9. 发明授权

US07027351B2 Negative word line driver 有权
标题翻译：负字线驱动
公开(公告)号：US07027351B2
公开(公告)日：2006-04-11
申请号：US10881056
申请日：2004-06-30
申请人： Kang Seol Lee , Yong Mi Kim
发明人： Kang Seol Lee , Yong Mi Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： Provided is directed to a negative word line driver, including: a block select address generation unit for generating first and second block select addresses having a block information according to an active signal; a row decoder controller for generating a control signal to disable a word line; a main word line driver for accessing a main word line by being driven in response to a signal coding the first block select address and the control signal; and a phi X driver for accessing a sub word line by being driven in response to a signal coding the second block select address and the control signal wloff.
摘要翻译：提供一种负字线驱动器，包括：块选择地址生成单元，用于根据有效信号产生具有块信息的第一和第二块选择地址; 行解码器控制器，用于产生禁止字线的控制信号; 主字线驱动器，用于响应于对第一块选择地址和控制信号进行编码的信号被驱动来访问主字线; 以及用于通过响应于编码第二块选择地址和控制信号wloff的信号来驱动来访问子字线的phi X驱动器。

10. 发明申请

US20130082755A1 FILTERING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 有权
标题翻译：滤波电路和具有该电路的半导体集成电路
公开(公告)号：US20130082755A1
公开(公告)日：2013-04-04
申请号：US13302167
申请日：2011-11-22
申请人： Hye-Young LEE , Yong-Mi KIM
发明人： Hye-Young LEE , Yong-Mi KIM
IPC分类号： H03L7/06 , H03K5/00
CPC分类号： H03L7/0814 , H03K2005/00241 , H03L7/0816 , H03L7/093
摘要： A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.
摘要翻译：滤波电路包括：抖动判定基准控制部，被配置为根据操作模式确定抖动判定基准，响应抖动判定基准输出控制信号;滤波部，被配置为响应于抖动判定基准控制信号，并且响应于所设置的抖动判定参考，确定在采样周期期间是否维持输入信号。

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