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1. 发明申请

US20060146218A1 Array substrate and a display apparatus having the same 有权
标题翻译：阵列基板和具有该基板的显示装置
公开(公告)号：US20060146218A1
公开(公告)日：2006-07-06
申请号：US11291366
申请日：2005-12-01
申请人： Yong-Koo Her , Jin Jeon , Yong-Han Park , Sang-Hoon Lee , Ji-Suk Lim
发明人： Yong-Koo Her , Jin Jeon , Yong-Han Park , Sang-Hoon Lee , Ji-Suk Lim
IPC分类号： G02F1/136
CPC分类号： H01L27/1255 , G02F1/134363 , G02F1/1368 , H01L27/1214 , H01L29/786
摘要： An array substrate and a display apparatus including the array substrate are provided. The array substrate includes a substrate divided into a display area and a peripheral area adjacent to the display area. A pixel array is formed on the substrate corresponding to the display area and receives a driving signal. A driving circuit includes a plurality of stages and is formed on the substrate corresponding to the peripheral area. Each of the stages includes a first transistor having a source electrode connected to an output terminal to output the driving signal, a channel layer formed between a gate insulating layer and the source electrode, the channel layer having an opening to facilitate contact between a portion of the gate insulating layer and the source electrode, and a capacitor defined by a gate electrode of the first transistor, the source electrode, and the gate insulating layer contacting the source electrode.
摘要翻译：提供了阵列基板和包括阵列基板的显示装置。阵列基板包括分为显示区域和与显示区域相邻的外围区域的基板。在对应于显示区域的基板上形成像素阵列并接收驱动信号。驱动电路包括多个级，并且形成在与外围区域对应的基板上。每个级包括第一晶体管，其源极连接到输出端以输出驱动信号，沟道层形成在栅极绝缘层和源电极之间，沟道层具有开口以便于部分栅绝缘层和源电极以及由第一晶体管的栅电极，源电极和与源电极接触的栅绝缘层限定的电容器。

2. 发明授权

US08493524B2 Array substrate having a gate driving circuit with an improved output characteristic and a display apparatus having the same 有权
标题翻译：具有具有改善的输出特性的栅极驱动电路的阵列基板和具有该栅极驱动电路的显示装置
公开(公告)号：US08493524B2
公开(公告)日：2013-07-23
申请号：US11291366
申请日：2005-12-01
申请人： Yong-Koo Her , Jin Jeon , Yong-Han Park , Sang-Hoon Lee , Ji-Suk Lim
发明人： Yong-Koo Her , Jin Jeon , Yong-Han Park , Sang-Hoon Lee , Ji-Suk Lim
IPC分类号： G02F1/136 , H01L31/101 , H01L27/088
CPC分类号： H01L27/1255 , G02F1/134363 , G02F1/1368 , H01L27/1214 , H01L29/786
摘要： An array substrate and a display apparatus including the array substrate are provided. The array substrate includes a substrate divided into a display area and a peripheral area adjacent to the display area. A pixel array is formed on the substrate corresponding to the display area and receives a driving signal. A driving circuit includes a plurality of stages and is formed on the substrate corresponding to the peripheral area. Each of the stages includes a first transistor having a source electrode connected to an output terminal to output the driving signal, a channel layer formed between a gate insulating layer and the source electrode, the channel layer having an opening to facilitate contact between a portion of the gate insulating layer and the source electrode, and a capacitor defined by a gate electrode of the first transistor, the source electrode, and the gate insulating layer contacting the source electrode.
摘要翻译：提供了阵列基板和包括阵列基板的显示装置。阵列基板包括分为显示区域和与显示区域相邻的外围区域的基板。在对应于显示区域的基板上形成像素阵列并接收驱动信号。驱动电路包括多个级，并且形成在与外围区域对应的基板上。每个级包括第一晶体管，其源极连接到输出端以输出驱动信号，沟道层形成在栅极绝缘层和源电极之间，沟道层具有开口以便于部分栅绝缘层和源电极以及由第一晶体管的栅电极，源电极和与源电极接触的栅绝缘层限定的电容器。

3. 发明授权

US09343475B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09343475B2
公开(公告)日：2016-05-17
申请号：US14155842
申请日：2014-01-15
申请人： Kyung-Tae Jang , Sang-Hoon Lee , Ji-Youn Seo , Hyun-Yong Go , Koong-Hyun Nam , Ju-Wan Kim , Seung-Mok Shin , Myoung-Bum Lee , Ji-Woon Im , Tae-Jong Han
发明人： Kyung-Tae Jang , Sang-Hoon Lee , Ji-Youn Seo , Hyun-Yong Go , Koong-Hyun Nam , Ju-Wan Kim , Seung-Mok Shin , Myoung-Bum Lee , Ji-Woon Im , Tae-Jong Han
IPC分类号： H01L21/336 , H01L27/115 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157
摘要： In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
摘要翻译：在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。然后，可以扩大孔的内部。半导体图案形成为部分地填充孔的扩大部分。可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。牺牲层被栅电极代替。

4. 发明申请

US20150200203A1 Vertical Memory Devices and Methods of Manufacturing the Same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20150200203A1
公开(公告)日：2015-07-16
申请号：US14155842
申请日：2014-01-15
申请人： Kyung-Tae Jang , Sang-Hoon Lee , Ji-Youn Seo , Hyun-Yong Go , Koong-Hyun Nam , Ju-Wan Kim , Seung-Mok Shin , Myoung-Bum Lee , Ji-Woon Im , Tae-Jong Han
发明人： Kyung-Tae Jang , Sang-Hoon Lee , Ji-Youn Seo , Hyun-Yong Go , Koong-Hyun Nam , Ju-Wan Kim , Seung-Mok Shin , Myoung-Bum Lee , Ji-Woon Im , Tae-Jong Han
IPC分类号： H01L27/115 , H01L29/66 , H01L29/788 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157
摘要： In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
摘要翻译：在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。然后，可以扩大孔的内部。半导体图案形成为部分地填充孔的扩大部分。可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。牺牲层被栅电极代替。

5. 发明授权

US08606102B2 Test interface device, test system and optical interface memory device 有权
标题翻译：测试接口设备，测试系统和光接口存储设备
公开(公告)号：US08606102B2
公开(公告)日：2013-12-10
申请号：US12592817
申请日：2009-12-03
申请人： Sang-Hoon Lee , Eun-Jo Byun , Cheol-Jong Woo , Se-Jang Oh
发明人： Sang-Hoon Lee , Eun-Jo Byun , Cheol-Jong Woo , Se-Jang Oh
IPC分类号： H04B10/08 , H04B17/00
CPC分类号： G11C29/56 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： A test interface device includes a serializer, an optical transmitter, an optical receiver, and a deserializer. The serializer receives parallel test signals from automatic test equipment, and serializes the parallel test signals into a serial test signal. The optical transmitter converts the serial test signal into an optical test signal. The optical receiver receives the optical test signal from the optical transmitter, and converts the optical test signal into the serial test signal. The deserializer deserializes the serial test signal into the parallel test signals, and transmits the parallel test signals to a device under test. As a result, signal transfer speed may be improved and optical resource usage may be reduced.
摘要翻译：测试接口设备包括串行器，光发送器，光接收器和解串器。串行器从自动测试设备接收并行测试信号，将并行测试信号串行化为串行测试信号。光发射机将串行测试信号转换为光学测试信号。光接收机从光发射机接收光测试信号，并将光测试信号转换为串行测试信号。解串器将串行测试信号反序列化为并行测试信号，并将并行测试信号发送到被测设备。结果，可以提高信号传送速度，并且可以减少光学资源的使用。

6. 发明授权

US08510951B2 Method for producing a lens pattern on roll 失效
标题翻译：用于在辊上制造透镜图案的方法
公开(公告)号：US08510951B2
公开(公告)日：2013-08-20
申请号：US12549638
申请日：2009-08-28
申请人： Hee-Cheong Lee , Sang-Hoon Lee , Jun-Sang Park , Tae-Yong Ryu
发明人： Hee-Cheong Lee , Sang-Hoon Lee , Jun-Sang Park , Tae-Yong Ryu
IPC分类号： B29C59/04
CPC分类号： G02B3/0018 , Y10T29/4956 , Y10T29/49563 , Y10T428/24917
摘要： The present disclosure generally relates to a method for producing lens patterns on a roll which is used to produce optical films wherein the method comprises forming a resin film on a roll comprising a plated layer which has been surface-plated with copper (Cu) or nickel (Ni); producing a preliminary lens pattern by striking the surface of the resin film on the roll with a chisel; etching with an etching solution the roll having the preliminary lens pattern formed thereon; and removing the resin film, and a roll for producing optical films comprising lens patterns formed thereon by the same method.
摘要翻译：本公开总体上涉及用于制造光学膜的辊上的透镜图案的方法，其中所述方法包括在辊上形成树脂膜，所述辊包括已经用铜（Cu）或镍表面镀覆的镀层（Ni）; 通过用凿子将辊上的树脂膜的表面撞击来产生预备的透镜图案; 用蚀刻溶液蚀刻其上形成有预备透镜图案的辊; 并除去树脂膜，以及用于制造包括通过相同方法形成在其上的透镜图案的光学膜的辊。

7. 发明申请

US20120266809A1 INSULATION DEVICE OF SINGLE CRYSTAL GROWTH DEVICE AND SINGLE CRYSTAL GROWTH DEVICE INCLUDING THE SAME 审中-公开
标题翻译：单晶生长装置的绝缘装置和包括其的单晶生长装置
公开(公告)号：US20120266809A1
公开(公告)日：2012-10-25
申请号：US13542590
申请日：2012-07-05
申请人： Sang-Hoon Lee , Hyun-Jung Oh , Il-Soo Choi
发明人： Sang-Hoon Lee , Hyun-Jung Oh , Il-Soo Choi
IPC分类号： C30B15/00
CPC分类号： C30B35/00 , C30B11/003 , C30B15/14 , Y10T117/1068
摘要： Provides are an insulation device of a single crystal growth device and a single crystal growth device including the same. The insulation device is installed inside a chamber of the single crystal growth device and the insulation device includes a plurality of insulation blocks that are spaced by a first distance.
摘要翻译：提供单晶生长装置的绝缘装置和包括其的单晶生长装置。绝缘装置安装在单晶生长装置的室内，并且绝缘装置包括间隔第一距离的多个绝缘块。

8. 发明授权

US08054044B2 Apparatus and method for balancing of battery cell'S charge capacity 有权
标题翻译：用于平衡电池电池容量的装置和方法
公开(公告)号：US08054044B2
公开(公告)日：2011-11-08
申请号：US12444712
申请日：2008-07-28
申请人： Ju-Hyun Kang , Do-Youn Kim , Sang-Hoon Lee
发明人： Ju-Hyun Kang , Do-Youn Kim , Sang-Hoon Lee
IPC分类号： H02J7/00
CPC分类号： H02J7/0016 , Y02T10/7055
摘要： An apparatus for balancing charge capacity of battery cell includes a voltage sensing/discharging circuit having a battery with cell group, a switching unit for selectively connecting both terminals of each battery cell to conductive lines, capacitor connected to the conductive lines, a voltage amplifying unit connected to both terminals of capacitor via a first switch, and a discharge resistance connected to both terminals of capacitor via a second switch; and a voltage balancing unit for controlling the switching unit in ON state of first switch to connect both terminals of each battery cell to the conductive lines and then sense voltage of each battery cell through the voltage amplifying unit, and controlling the switching unit in OFF state of first switch to charge voltage of balancing-requiring cell to the capacitor and then turning on the second switch to discharge charged voltage of capacitor through the discharge resistance.
摘要翻译：用于平衡电池单元的充电容量的装置包括具有电池组的电压感测/放电电路，用于选择性地将每个电池单元的端子与导线相连的开关单元，连接到导线的电容器，电压放大单元经由第一开关连接到电容器的两个端子，以及经由第二开关连接到电容器两端的放电电阻; 以及电压平衡单元，用于将开关单元控制在第一开关的接通状态，以将每个电池单元的两个端子连接到导线，然后通过电压放大单元感测每个电池单元的电压，并将开关单元控制在OFF状态首先切换到平衡需求单元的电荷到电容器，然后接通第二开关以通过放电电阻放电电容器的充电电压。

9. 发明申请

US20110221715A1 FLAT PANEL DISPLAY DEVICE AND METHOD FOR DRIVING THEREOF 审中-公开
标题翻译：平板显示装置及其驱动方法
公开(公告)号：US20110221715A1
公开(公告)日：2011-09-15
申请号：US13037590
申请日：2011-03-01
申请人： Jin-Wook Yang , Sang-Jae Yeo , Sang-Hoon Lee
发明人： Jin-Wook Yang , Sang-Jae Yeo , Sang-Hoon Lee
IPC分类号： G06F3/038 , G02F1/133 , G02F1/1368 , G09G3/36
CPC分类号： G02F1/13454 , G02F1/136286 , G09G3/3648 , G09G2300/0439
摘要： A flat panel display device is disclosed. In some embodiments, the flat panel display device has parallel gate and data lines in a display area. In some embodiments, all sub-pixels of each pixel are connected to the same data line and are connected to the same gate line.
摘要翻译：公开了一种平板显示装置。在一些实施例中，平板显示装置在显示区域中具有并行栅极和数据线。在一些实施例中，每个像素的所有子像素连接到相同的数据线并连接到相同的栅极线。

10. 发明授权

US07973550B2 Semiconductor device test apparatus including interface unit and method of testing semiconductor device using the same 有权
标题翻译：包括接口单元的半导体器件测试装置和使用其的半导体器件的测试方法
公开(公告)号：US07973550B2
公开(公告)日：2011-07-05
申请号：US12582980
申请日：2009-10-21
申请人： Eun-Jo Byun , Sang-Hoon Lee , Se-Jang Oh , Cheol-Jong Woo
发明人： Eun-Jo Byun , Sang-Hoon Lee , Se-Jang Oh , Cheol-Jong Woo
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/31932 , G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： A semiconductor device test apparatus is provided. The semiconductor device test apparatus includes a test unit on which a semiconductor device under test is disposed, and an automatic test equipment (ATE) unit that inputs a test signal to the test unit and reads a test result signal output by the test unit. The semiconductor device test apparatus includes an interface unit that is interposed between the test unit and the ATE unit, and that compares the test signal with the test result signal and outputs to the ATE unit comparison signals indicating whether the semiconductor device is a failure or not or whether a specific bit failure has occurred or not.
摘要翻译：提供一种半导体器件测试装置。半导体器件测试装置包括一个测试单元，在该测试单元上设置有被测半导体器件，以及一个自动测试设备（ATE）单元，它将测试信号输入到测试单元并读取由测试单元输出的测试结果信号。半导体器件测试装置包括插入在测试单元和ATE单元之间的接口单元，并且将测试信号与测试结果信号进行比较，并输出到指示半导体器件是否为故障的ATE单元比较信号或者是否发生特定位故障。

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