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1. 发明申请

US20060197573A1 Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路及半导体集成电路制造方法
公开(公告)号：US20060197573A1
公开(公告)日：2006-09-07
申请号：US11365604
申请日：2006-03-02
申请人： Yoichi Matsumura , Takako Ohashi , Fumihiro Kimura , Kiyohito Mukai , Masanori Itou
发明人： Yoichi Matsumura , Takako Ohashi , Fumihiro Kimura , Kiyohito Mukai , Masanori Itou
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G01R31/2856
摘要： The semiconductor integrated circuit of the present invention comprises a clock circuit for generating a clock signal. The clock circuit comprises a clock control circuit for controlling propagation of the clock signal. The clock control circuit comprises a burn-in control signal input terminal for inputting a burn-in control signal that controls operation state of the clock circuit when performing burn-in processing, and a clock control signal output terminal for outputting the clock signal. The clock control circuit controls propagation of the clock signal outputted from the clock control signal output terminal based on the burn-in control signal inputted to the burn-in control signal input terminal.
摘要翻译：本发明的半导体集成电路包括用于产生时钟信号的时钟电路。时钟电路包括用于控制时钟信号传播的时钟控制电路。该时钟控制电路包括一个老化控制信号输入端，用于输入一个控制时钟电路在进行老化处理时的运行状态的老化控制信号，以及一个用于输出时钟信号的时钟控制信号输出端。时钟控制电路基于输入到老化控制信号输入端子的老化控制信号，控制从时钟控制信号输出端子输出的时钟信号的传播。

2. 发明授权

US07174527B2 Layout verification method and method for designing semiconductor integrated circuit device using the same 有权
标题翻译：使用该半导体集成电路器件的布局验证方法和设计方法
公开(公告)号：US07174527B2
公开(公告)日：2007-02-06
申请号：US11270594
申请日：2005-11-10
申请人： Masanori Itou , Kiyohito Mukai
发明人： Masanori Itou , Kiyohito Mukai
IPC分类号： G06F17/50
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： To provide a layout verification method capable of accurately detecting damage to be given to a gate, and to provide a higher-workability and higher-reliability design method to accurately detect damage to be given to a gate and to determine an approach for design correction to avoid damage, the layout verification method according to the invention is characterized in that an antenna value which is an estimated value of transistor gate damage is output based on an antenna ratio, and a fluctuation of plasma charging damage due to the layout near the transistor gate.
摘要翻译：为了提供能够准确地检测给予门的损害的布局验证方法，并且提供更高的可操作性和更高可靠性的设计方法来准确地检测给予门的损坏并且确定用于设计校正的方法避免损坏，根据本发明的布局验证方法的特征在于，基于天线比输出作为晶体管栅极损坏的估计值的天线值，以及由于晶体管栅极附近的布局引起的等离子体充电损坏的波动。

3. 发明申请

US20060115911A1 Layout verification method and method for designing semiconductor integrated circuit device using the same 有权
标题翻译：使用该半导体集成电路器件的布局验证方法和设计方法
公开(公告)号：US20060115911A1
公开(公告)日：2006-06-01
申请号：US11270594
申请日：2005-11-10
申请人： Masanori Itou , Kiyohito Mukai
发明人： Masanori Itou , Kiyohito Mukai
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： To provide a layout verification method capable of accurately detecting damage to be given to a gate, and to provide a higher-workability and higher-reliability design method to accurately detect damage to be given to a gate and to determine an approach for design correction to avoid damage, the layout verification method according to the invention is characterized in that an antenna value which is an estimated value of transistor gate damage is output based on an antenna ratio, and a fluctuation of plasma charging damage due to the layout near the transistor gate.
摘要翻译：为了提供能够准确地检测给予门的损害的布局验证方法，并且提供更高的可操作性和更高可靠性的设计方法来准确地检测给予门的损坏并且确定用于设计校正的方法避免损坏，根据本发明的布局验证方法的特征在于，基于天线比输出作为晶体管栅极损坏的估计值的天线值，以及由于晶体管栅极附近的布局引起的等离子体充电损坏的波动。

4. 发明申请

US20050172248A1 Area ratio/occupancy ratio verification method and pattern generation method 有权
标题翻译：面积比/占有率验证方法和图案生成方法
公开(公告)号：US20050172248A1
公开(公告)日：2005-08-04
申请号：US10886704
申请日：2004-07-09
申请人： Junichi Shimada , Fumihiro Kimura , Mitsumi Ito , Kiyohito Mukai
发明人： Junichi Shimada , Fumihiro Kimura , Mitsumi Ito , Kiyohito Mukai
IPC分类号： G06F17/50 , G06F9/45 , H01L21/3205 , H01L21/82 , H01L23/52
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.
摘要翻译：假设半导体集成电路器件的模式面积比的验证或半导体集成电路器件设置的检查窗口中的图案占有率是在将半导体集成电路器件的未占用区域放置在由半导体集成电路器件的未占用区域集成电路器件或在半导体集成电路器件中设置的至少一个实例中的未占用区域中。

5. 发明授权

US07269807B2 Area ratio/occupancy ratio verification method and pattern generation method 有权
标题翻译：面积比/占有率验证方法和图案生成方法
公开(公告)号：US07269807B2
公开(公告)日：2007-09-11
申请号：US10886704
申请日：2004-07-09
申请人： Junichi Shimada , Fumihiro Kimura , Mitsumi Ito , Kiyohito Mukai
发明人： Junichi Shimada , Fumihiro Kimura , Mitsumi Ito , Kiyohito Mukai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.
摘要翻译：在半导体集成电路器件设定的检查窗口中，对半导体集成电路器件的图案面积比率或图案占有率的验证是在将由工艺条件限定的虚设图案置于半导体集成电路的未占用区域中的假设下进行的集成电路器件或在半导体集成电路器件中提供的至少一个实例中的未占用区域中。

6. 发明申请

US20070020880A1 Method of fabricating a semiconductor device and a method of generating a mask pattern 失效
标题翻译：制造半导体器件的方法和产生掩模图案的方法
公开(公告)号：US20070020880A1
公开(公告)日：2007-01-25
申请号：US11522995
申请日：2006-09-19
申请人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
发明人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , G06F17/5068 , H01L21/76229
摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.
摘要翻译：至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。在包括凹槽内部的半导体衬底的表面上形成绝缘膜。使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜形成在第二区域中。在这两种情况下，剩余的绝缘膜被抛光。

7. 发明申请

US20050204327A1 Layout data verification method, mask pattern verification method and circuit operation verification method 审中-公开
标题翻译：布局数据验证方法，掩模图案验证方法和电路操作验证方法
公开(公告)号：US20050204327A1
公开(公告)日：2005-09-15
申请号：US11076939
申请日：2005-03-11
申请人： Kiyohito Mukai , Mitsumi Itou , Ritsuko Ozoe , Tatsuo Ohashi , Hiroyuki Tsujikawa
发明人： Kiyohito Mukai , Mitsumi Itou , Ritsuko Ozoe , Tatsuo Ohashi , Hiroyuki Tsujikawa
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , H01L21/82
CPC分类号： G03F1/70 , G03F7/705
摘要： In the verification method of the present invention, a defect that is to cause a problem in fabrication is extracted from a mask pattern. The mask pattern is one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern. The verification method includes the steps of: determining the exposure dose in the photolithography process; simulating the photolithography process on a computer based on the determined exposure dose; checking whether or not the desired design pattern has been obtained; and locating a fault point and outputting the result.
摘要翻译：在本发明的验证方法中，从掩模图案中提取出导致制造中的问题的缺陷。掩模图案是通过使用于光刻工艺中的光掩模的掩模图案变形而获得的，以便提供接近所需设计图案的转印图像。验证方法包括以下步骤：确定光刻工艺中的曝光剂量; 基于所确定的曝光剂量在计算机上模拟光刻工艺; 检查是否获得了所需的设计图案; 并定位故障点并输出结果。

8. 发明授权

US07707523B2 Method of fabricating a semiconductor device and a method of generating a mask pattern 失效
标题翻译：制造半导体器件的方法和产生掩模图案的方法
公开(公告)号：US07707523B2
公开(公告)日：2010-04-27
申请号：US11522995
申请日：2006-09-19
申请人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
发明人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
IPC分类号： G06F17/50
CPC分类号： H01L21/31053 , G06F17/5068 , H01L21/76229
摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.
摘要翻译：至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。在包括凹槽内部的半导体衬底的表面上形成绝缘膜。使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜形成在第二区域中。在这两种情况下，剩余的绝缘膜被抛光。

9. 发明授权

US06183920B2 Semiconductor device geometrical pattern correction process and geometrical pattern extraction process 失效
标题翻译：半导体器件几何图案校正过程和几何图案提取过程
公开(公告)号：US06183920B2
公开(公告)日：2001-02-06
申请号：US09348316
申请日：1999-07-07
申请人： Hiroyuki Tsujikawa , Hidenori Shibata , Kiyohito Mukai
发明人： Hiroyuki Tsujikawa , Hidenori Shibata , Kiyohito Mukai
IPC分类号： G03F900
CPC分类号： G03F7/70441 , G03F1/36
摘要： A semiconductor device geometrical pattern correction process, semiconductor device manufacturing process and geometrical pattern extraction process are provided, which make it possible to eliminate the adverse effect of corner rounding accompanying miniaturization, that is, a decrease in the projection amount of a gate, while avoiding increased chip area. The correction process comprises a step 102 of detecting a concave diffusion layer corresponding portion and a step 103 of correcting either the concave diffusion layer corresponding portion or a transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion in order to ensure the projection of the gate from the concave diffusion layer corresponding portion against possible corner rounding.
摘要翻译：提供半导体器件几何图案校正处理，半导体器件制造工艺和几何图案提取处理，这可以消除伴随着小型化的圆角倒圆的不良影响，即，避免浇口的投影量的减少，同时避免增加芯片面积。校正处理包括检测凹面扩散层对应部分的步骤102和校正从凹形扩散层对应部分突出的凹形扩散层对应部分或晶体管栅极对应部分的步骤103，以确保投影来自凹面扩散层的对应部分的栅极可能围绕可能的角落四舍五入。

10. 发明授权

US07115478B2 Method of fabricating a semiconductor device and a method of generating a mask pattern 有权
标题翻译：制造半导体器件的方法和产生掩模图案的方法
公开(公告)号：US07115478B2
公开(公告)日：2006-10-03
申请号：US10663642
申请日：2003-09-17
申请人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
发明人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , G06F17/5068 , H01L21/76229
摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.
摘要翻译：至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。在包括凹槽内部的半导体衬底的表面上形成绝缘膜。使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜形成在第二区域中。在这两种情况下，剩余的绝缘膜被抛光。

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