专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050204327A1 Layout data verification method, mask pattern verification method and circuit operation verification method 审中-公开
标题翻译：布局数据验证方法，掩模图案验证方法和电路操作验证方法
公开(公告)号：US20050204327A1
公开(公告)日：2005-09-15
申请号：US11076939
申请日：2005-03-11
申请人： Kiyohito Mukai , Mitsumi Itou , Ritsuko Ozoe , Tatsuo Ohashi , Hiroyuki Tsujikawa
发明人： Kiyohito Mukai , Mitsumi Itou , Ritsuko Ozoe , Tatsuo Ohashi , Hiroyuki Tsujikawa
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , H01L21/82
CPC分类号： G03F1/70 , G03F7/705
摘要： In the verification method of the present invention, a defect that is to cause a problem in fabrication is extracted from a mask pattern. The mask pattern is one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern. The verification method includes the steps of: determining the exposure dose in the photolithography process; simulating the photolithography process on a computer based on the determined exposure dose; checking whether or not the desired design pattern has been obtained; and locating a fault point and outputting the result.
摘要翻译：在本发明的验证方法中，从掩模图案中提取出导致制造中的问题的缺陷。掩模图案是通过使用于光刻工艺中的光掩模的掩模图案变形而获得的，以便提供接近所需设计图案的转印图像。验证方法包括以下步骤：确定光刻工艺中的曝光剂量; 基于所确定的曝光剂量在计算机上模拟光刻工艺; 检查是否获得了所需的设计图案; 并定位故障点并输出结果。

2. 发明授权

US06183920B2 Semiconductor device geometrical pattern correction process and geometrical pattern extraction process 失效
标题翻译：半导体器件几何图案校正过程和几何图案提取过程
公开(公告)号：US06183920B2
公开(公告)日：2001-02-06
申请号：US09348316
申请日：1999-07-07
申请人： Hiroyuki Tsujikawa , Hidenori Shibata , Kiyohito Mukai
发明人： Hiroyuki Tsujikawa , Hidenori Shibata , Kiyohito Mukai
IPC分类号： G03F900
CPC分类号： G03F7/70441 , G03F1/36
摘要： A semiconductor device geometrical pattern correction process, semiconductor device manufacturing process and geometrical pattern extraction process are provided, which make it possible to eliminate the adverse effect of corner rounding accompanying miniaturization, that is, a decrease in the projection amount of a gate, while avoiding increased chip area. The correction process comprises a step 102 of detecting a concave diffusion layer corresponding portion and a step 103 of correcting either the concave diffusion layer corresponding portion or a transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion in order to ensure the projection of the gate from the concave diffusion layer corresponding portion against possible corner rounding.
摘要翻译：提供半导体器件几何图案校正处理，半导体器件制造工艺和几何图案提取处理，这可以消除伴随着小型化的圆角倒圆的不良影响，即，避免浇口的投影量的减少，同时避免增加芯片面积。校正处理包括检测凹面扩散层对应部分的步骤102和校正从凹形扩散层对应部分突出的凹形扩散层对应部分或晶体管栅极对应部分的步骤103，以确保投影来自凹面扩散层的对应部分的栅极可能围绕可能的角落四舍五入。

3. 发明申请

US20050224914A1 Semiconductor integrated circuit device, method of enerating pattern thereof, method of manufacturing the same, and pattern generating apparatus for the same 审中-公开
标题翻译：半导体集成电路装置及其图案的制造方法，制造方法以及图案生成装置
公开(公告)号：US20050224914A1
公开(公告)日：2005-10-13
申请号：US11103490
申请日：2005-04-12
申请人： Kiyohito Mukai , Hiroyuki Tsujikawa
发明人： Kiyohito Mukai , Hiroyuki Tsujikawa
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/04 , H01L27/08 , H01L31/0392
CPC分类号： H01L23/5223 , H01L23/5286 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： To provide a semiconductor integrated circuit device capable of effectively absorbing power supply noise, of achieving the stable operation of a circuit, and particularly, of absorbing noise in a vicinity of a noise generating source. The semiconductor integrated circuit device has at least one circuit block. The semiconductor integrated circuit device includes a bypass capacitor having a first conductor layer 1a formed on the circuit block and a second conductor layer 1b formed on the first conductor layer 1a with a capacitor insulating film 1c interposed therebetween. One of the first and second conductor layers of the bypass capacitor is connected to one of a grounding wiring line or a power supply wiring lines through a substrate contact which fixes a potential of a substrate and the other is connected to the other of the power supply wiring line or the grounding wiring line.
摘要翻译：提供能够有效地吸收电源噪声的半导体集成电路器件，实现电路的稳定操作，特别是在噪声产生源附近吸收噪声。半导体集成电路器件具有至少一个电路块。半导体集成电路器件包括：旁路电容器，其具有形成在电路块上的第一导体层1a和形成在第一导体层1a上的第二导体层1b，其间插入电容器绝缘膜1c。旁路电容器的第一和第二导体层之一通过固定基板的电位的基板触点而连接到接地布线或电源布线中的一个，另一个连接到电源的另一个接线或接地线。

4. 发明授权

US07171645B2 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device 有权
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置
公开(公告)号：US07171645B2
公开(公告)日：2007-01-30
申请号：US10634988
申请日：2003-08-06
申请人： Mitsumi Ito , Junichi Shimada , Kiyohito Mukai , Hiroyuki Tsujikawa
发明人： Mitsumi Ito , Junichi Shimada , Kiyohito Mukai , Hiroyuki Tsujikawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high.A method of generating a pattern for a semiconductor device comprises: a step of designing and arranging a layout pattern of a semiconductor chip; a step of extracting an area ratio of the mask pattern from the layout pattern; and a step of adding and arranging a dummy pattern to the layout pattern, while consideration is given to the most appropriate area ratio of the layout pattern of the layer obtained according to a process condition of the layer composing the layout pattern, so that the area ratio of the layer can be the most appropriate area ratio.
摘要翻译：为了提供能够形成高可靠性的半导体器件的半导体器件的图案生成方法，其精度高。一种生成用于半导体器件的图案的方法包括：设计和布置半导体芯片的布局图案的步骤; 从布局图案提取掩模图案的面积比的步骤; 以及向布局图案添加和布置虚拟图案的步骤，同时考虑根据构成布局图案的层的处理条件获得的层的布局图案的最合适面积比，使得区域该层的比例可以是最合适的面积比。

5. 发明授权

US07062732B2 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device 失效
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及用于半导体装置的图案的制造装置
公开(公告)号：US07062732B2
公开(公告)日：2006-06-13
申请号：US10634989
申请日：2003-08-06
申请人： Mitsumi Ito , Junichi Shimada , Kiyohito Mukai , Hiroyuki Tsujikawa
发明人： Mitsumi Ito , Junichi Shimada , Kiyohito Mukai , Hiroyuki Tsujikawa
IPC分类号： G06F9/45
CPC分类号： H01L23/585 , G06F17/5068 , H01L27/0203 , H01L2924/0002 , Y02T10/82 , H01L2924/00
摘要： To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation of a circuit can be realized.Irrespective of whether or not a region is close to a power supply wiring or a ground wiring, MOS is spread all over a spare area of a chip and connected to a power supply wiring and ground wiring by utilizing a wiring layer and diffusion layer.
摘要翻译：提供一种半导体器件，其特征在于：可以增加去耦电容器; 可以有效地吸收从电源产生的噪声; 并且可以实现电路的稳定操作。无论区域是否接近电源布线或接地布线，MOS都通过利用布线层和扩散层而遍布芯片的备用区域并与电源布线和接地布线相连。

6. 发明授权

US06303251B1 Mask pattern correction process, photomask and semiconductor integrated circuit device 失效
标题翻译：掩模图案校正工艺，光掩模和半导体集成电路器件
公开(公告)号：US06303251B1
公开(公告)日：2001-10-16
申请号：US09360989
申请日：1999-07-27
申请人： Kiyohito Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
发明人： Kiyohito Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
IPC分类号： G03F900
CPC分类号： G03F7/70441 , G03F1/36
摘要： In order that CAD processing time required for modifying an input design pattern to compensate for optical proximity effects is reduced, increases in the number of base shapes when corrected data are converted into EB data are restricted, and false detection of defects in a photomask inspection process is restricted, the following steps are taken. At a shape selection step, rectangular shapes are divided into a dense rectangular shape group and a non-dense rectangular shape group according to the distance of each rectangular shape to an adjacent rectangular shape. At a number-of-shapeas comparison step, the number of shapes included in the dense rectangular shape group is compared to the number of shapes included in the non-dense rectangular shape group to select either shape group for correction. At a correction process selection step, a correction process suited for the selected shape group is selected. At a shape correction step, optical proximity correction is made. At a shape combining step, a group of corrected shapes and the rectangular shape group different from the selected one are combined.
摘要翻译：为了减少修改输入设计图案以补偿光学邻近效应所需的CAD处理时间，校正数据被转换为EB数据时的基本形状数量的增加受到限制，并且光掩模检查过程中的缺陷的错误检测被限制，采取以下步骤。在形状选择步骤中，矩形形状根据每个矩形形状与相邻矩形形状的距离被分成致密矩形形状组和非密集矩形形状组。在数字形状比较步骤中，将包含在密集矩形形状组中的形状的数量与包括在非致密矩形形状组中的形状的数量进行比较，以选择用于校正的形状组。在校正处理选择步骤中，选择适合所选择的形状组的校正处理。在形状校正步骤中，进行光学邻近校正。在形状组合步骤中，组合一组校正形状和与所选择的形状组不同的矩形形状组合。

7. 发明申请

US20070020880A1 Method of fabricating a semiconductor device and a method of generating a mask pattern 失效
标题翻译：制造半导体器件的方法和产生掩模图案的方法
公开(公告)号：US20070020880A1
公开(公告)日：2007-01-25
申请号：US11522995
申请日：2006-09-19
申请人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
发明人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , G06F17/5068 , H01L21/76229
摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.
摘要翻译：至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。在包括凹槽内部的半导体衬底的表面上形成绝缘膜。使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜形成在第二区域中。在这两种情况下，剩余的绝缘膜被抛光。

8. 发明申请

US20060197573A1 Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路及半导体集成电路制造方法
公开(公告)号：US20060197573A1
公开(公告)日：2006-09-07
申请号：US11365604
申请日：2006-03-02
申请人： Yoichi Matsumura , Takako Ohashi , Fumihiro Kimura , Kiyohito Mukai , Masanori Itou
发明人： Yoichi Matsumura , Takako Ohashi , Fumihiro Kimura , Kiyohito Mukai , Masanori Itou
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G01R31/2856
摘要： The semiconductor integrated circuit of the present invention comprises a clock circuit for generating a clock signal. The clock circuit comprises a clock control circuit for controlling propagation of the clock signal. The clock control circuit comprises a burn-in control signal input terminal for inputting a burn-in control signal that controls operation state of the clock circuit when performing burn-in processing, and a clock control signal output terminal for outputting the clock signal. The clock control circuit controls propagation of the clock signal outputted from the clock control signal output terminal based on the burn-in control signal inputted to the burn-in control signal input terminal.
摘要翻译：本发明的半导体集成电路包括用于产生时钟信号的时钟电路。时钟电路包括用于控制时钟信号传播的时钟控制电路。该时钟控制电路包括一个老化控制信号输入端，用于输入一个控制时钟电路在进行老化处理时的运行状态的老化控制信号，以及一个用于输出时钟信号的时钟控制信号输出端。时钟控制电路基于输入到老化控制信号输入端子的老化控制信号，控制从时钟控制信号输出端子输出的时钟信号的传播。

9. 发明授权

US07707523B2 Method of fabricating a semiconductor device and a method of generating a mask pattern 失效
标题翻译：制造半导体器件的方法和产生掩模图案的方法
公开(公告)号：US07707523B2
公开(公告)日：2010-04-27
申请号：US11522995
申请日：2006-09-19
申请人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
发明人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
IPC分类号： G06F17/50
CPC分类号： H01L21/31053 , G06F17/5068 , H01L21/76229
摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.
摘要翻译：至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。在包括凹槽内部的半导体衬底的表面上形成绝缘膜。使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜形成在第二区域中。在这两种情况下，剩余的绝缘膜被抛光。

10. 发明授权

US07174527B2 Layout verification method and method for designing semiconductor integrated circuit device using the same 有权
标题翻译：使用该半导体集成电路器件的布局验证方法和设计方法
公开(公告)号：US07174527B2
公开(公告)日：2007-02-06
申请号：US11270594
申请日：2005-11-10
申请人： Masanori Itou , Kiyohito Mukai
发明人： Masanori Itou , Kiyohito Mukai
IPC分类号： G06F17/50
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： To provide a layout verification method capable of accurately detecting damage to be given to a gate, and to provide a higher-workability and higher-reliability design method to accurately detect damage to be given to a gate and to determine an approach for design correction to avoid damage, the layout verification method according to the invention is characterized in that an antenna value which is an estimated value of transistor gate damage is output based on an antenna ratio, and a fluctuation of plasma charging damage due to the layout near the transistor gate.
摘要翻译：为了提供能够准确地检测给予门的损害的布局验证方法，并且提供更高的可操作性和更高可靠性的设计方法来准确地检测给予门的损坏并且确定用于设计校正的方法避免损坏，根据本发明的布局验证方法的特征在于，基于天线比输出作为晶体管栅极损坏的估计值的天线值，以及由于晶体管栅极附近的布局引起的等离子体充电损坏的波动。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式