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1. 发明申请

US20070051995A1 MOS transistor cell and semiconductor device 审中-公开
标题翻译： MOS晶体管单元和半导体器件
公开(公告)号：US20070051995A1
公开(公告)日：2007-03-08
申请号：US11516516
申请日：2006-09-07
申请人： Masahiko Kumashiro , Tadashi Tanimoto
发明人： Masahiko Kumashiro , Tadashi Tanimoto
IPC分类号： H01L29/94
CPC分类号： H01L27/0203 , H01L29/4238
摘要： A MOS transistor cell having a salicide structure has a plurality of gate wires each formed as a straight line with a constant width. Each of the gate wires includes a P-channel gate terminal and an N-channel gate terminal. The P-side ends and the N-side ends of the gate wires are connected by means of respective two gate wire connecting portions at a boundary portion between the MOS transistor cell and another adjacent MOS transistor cell.
摘要翻译：具有硅化物结构的MOS晶体管单元具有多个栅极线，每个栅极线形成为具有恒定宽度的直线。每个栅极线包括P沟道栅极端子和N沟道栅极端子。栅极线的P侧端部和N侧端部通过MOS晶体管单元和另一个相邻的MOS晶体管单元之间的边界部分的两个栅极连接部连接。

2. 发明授权

US07707523B2 Method of fabricating a semiconductor device and a method of generating a mask pattern 失效
标题翻译：制造半导体器件的方法和产生掩模图案的方法
公开(公告)号：US07707523B2
公开(公告)日：2010-04-27
申请号：US11522995
申请日：2006-09-19
申请人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
发明人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
IPC分类号： G06F17/50
CPC分类号： H01L21/31053 , G06F17/5068 , H01L21/76229
摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.
摘要翻译：至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。在包括凹槽内部的半导体衬底的表面上形成绝缘膜。使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜形成在第二区域中。在这两种情况下，剩余的绝缘膜被抛光。

3. 发明申请

US20070174807A1 Semiconductor device manufacturing method, library used for the same, recording medium, and semiconductor device manufacturing system 审中-公开
标题翻译：半导体器件制造方法，用于相同的库，记录介质和半导体器件制造系统
公开(公告)号：US20070174807A1
公开(公告)日：2007-07-26
申请号：US11487970
申请日：2006-07-18
申请人： Masahiko Kumashiro , Tadashi Tanimoto
发明人： Masahiko Kumashiro , Tadashi Tanimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F7/70433
摘要： To provide a semiconductor device manufacturing method of making a pattern formation possible with high precision at a high speed, the same block can be completed by one process a cell by dividing the layout data into cells in the OPC processing step and then applying the OPC to each cell, and the OPC is applied only to the cell boundary portions after respective OPC-applied cells are arranged on the chip, so that a dimensional precision in vicinity of the cell boundaries can be ensured. Also, since the patterns on the cell boundary portions are caused to shrink uniformly, the OPC of the cell boundary portions can be simplified and thus the fast process can be applied.
摘要翻译：为了提供以高速度高精度地进行图案形成的半导体器件制造方法，可以通过在OPC处理步骤中将布局数据分割为单元格，然后将OPC应用于OPC来完成通过一个单元的处理来完成相同的块每个单元，并且在将各个OPC应用单元布置在芯片上之后，OPC仅应用于单元边界部分，从而可以确保单元边界附近的尺寸精度。此外，由于使单元边界部分上的图案均匀地收缩，可以简化单元边界部分的OPC，因此可以应用快速处理。

4. 发明授权

US07114144B2 Mask pattern inspecting method, inspection apparatus, inspecting data used therein and inspecting data generating method 有权
标题翻译：掩模图案检查方法，检查装置，检查数据，检查数据生成方法
公开(公告)号：US07114144B2
公开(公告)日：2006-09-26
申请号：US10722346
申请日：2003-11-26
申请人： Shinya Tokunaga , Hiroyuki Tsujikawa , Tadashi Tanimoto
发明人： Shinya Tokunaga , Hiroyuki Tsujikawa , Tadashi Tanimoto
IPC分类号： G06F17/50
CPC分类号： G03F1/84 , G03F7/70616 , G06T7/0004 , G06T2207/30148
摘要： A method of inspecting a photomask for a semiconductor integrated circuit formed based on drawing pattern data, includes the steps of classifying a drawing pattern of the semiconductor integrated circuit into a plurality of ranks in accordance with a predetermined reference and extracting the same, determining inspecting accuracy for each of the ranks, and deciding quality of the photomask depending on whether the determined inspecting accuracy is satisfied.
摘要翻译：一种检查基于绘制图形数据形成的半导体集成电路的光掩模的方法，包括以下步骤：根据预定的参考将半导体集成电路的绘制图案分类成多个等级并提取它们，并提取它们，确定检查精度并且根据所确定的检查精度是否满足来确定光掩模的质量。

5. 发明授权

US5236885A Sheets for taking prints and a method of taking prints 失效
标题翻译：打印纸和打印的方法
公开(公告)号：US5236885A
公开(公告)日：1993-08-17
申请号：US799097
申请日：1991-11-27
申请人： Tadashi Tanimoto
发明人： Tadashi Tanimoto
IPC分类号： A61B5/117 , B41M5/128
CPC分类号： B41M5/128
摘要： Disclosed are a sheet for taking a print of an object, the sheet comprising (a) a substrate, and (b) a coating layer formed over the whole surface or part of the surface of the substrate and comprising a colorless or pale-colored basic dye, a color developing material which develops a color on contact with the dye and an adhesive, the whole of the coating layer being colored by the color-forming reaction of the basic dye and the color developing material; a method of taking a print of an object with use of the sheet comprising applying a desensitizer to the object and contacting the desensitizer with the sheet; and a kit for this purpose comprising the sheet and a desensitizer.
摘要翻译：公开了一种用于拍摄物体的印刷品，该片材包括（a）基材，和（b）在基材的整个表面或整个表面的一部分上形成的涂层，其包含无色或浅色的碱染料，与染料接触形成颜色的彩色显影剂和粘合剂，整个涂层通过碱性染料和彩色显影材料的着色反应着色; 使用该片材拍摄物体的印刷物的方法，包括对所述物体施加脱敏剂并使所述脱敏剂与所述片材接触; 以及用于该目的的试剂盒，包括片材和脱敏剂。

6. 发明授权

US07337423B2 Mask pattern generating method and mask pattern generating apparatus 失效
标题翻译：掩模图案生成方法和掩模图案生成装置
公开(公告)号：US07337423B2
公开(公告)日：2008-02-26
申请号：US10778337
申请日：2004-02-17
申请人： Minoru Yamagiwa , Tadashi Tanimoto , Akio Misaka , Reiko Hinogami
发明人： Minoru Yamagiwa , Tadashi Tanimoto , Akio Misaka , Reiko Hinogami
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Established is a mask pattern correcting technique for reducing the load to a mask CAD process and for ensuring the minimum dimension defined in an OPC process. A method comprises the steps of: measuring a line width of a mask pattern; extracting edges where the line width of the mask pattern is smaller than a predetermined dimension; generating a central geometrical object having a predetermined width relative to the center between the edges where the line width is smaller than the predetermined dimension; and replacing the portion of the mask pattern where the line width is smaller than the predetermined dimension with the central geometrical object. As a result, the mask pattern line width is changed into the predetermined with dimension of the central geometrical object. This reduces notably the number of geometrical object calculating steps that had been performed for each value of dimension on the basis of a correction table in the prior art, and thereby shortens the mask CAD processing time.
摘要翻译：建立了一种掩模图案校正技术，用于减少掩模CAD过程的负载并确保OPC过程中定义的最小尺寸。一种方法包括以下步骤：测量掩模图案的线宽; 提取掩模图案的线宽小于预定尺寸的边缘; 产生相对于所述线宽小于所述预定尺寸的边缘之间的中心具有预定宽度的中心几何物体; 并且用中心几何物体代替线宽小于预定尺寸的掩模图案的部分。结果，掩模图案线宽度变为具有中心几何对象的预定尺寸。这显着地减少了基于现有技术的校正表对每个维度值执行的几何对象计算步骤的数量，从而缩短了掩模CAD处理时间。

7. 发明申请

US20070009147A1 Mask pattern inspecting method, inspection apparatus, inspecting data used therein and inspecting data generating method 审中-公开
标题翻译：掩模图案检查方法，检查装置，检查数据，检查数据生成方法
公开(公告)号：US20070009147A1
公开(公告)日：2007-01-11
申请号：US11518198
申请日：2006-09-11
申请人： Shinya Tokunaga , Hiroyuki Tsujikawa , Tadashi Tanimoto
发明人： Shinya Tokunaga , Hiroyuki Tsujikawa , Tadashi Tanimoto
IPC分类号： G06K9/00
CPC分类号： G03F1/84 , G03F7/70616 , G06T7/0004 , G06T2207/30148
摘要： A method of inspecting a photomask for a semiconductor integrated circuit formed based on drawing pattern data, includes the steps of classifying a drawing pattern of the semiconductor integrated circuit into a plurality of ranks in accordance with a predetermined reference and extracting the same, determining inspecting accuracy for each of the ranks, and deciding quality of the photomask depending on whether the determined inspecting accuracy is satisfied.
摘要翻译：一种检查基于绘制图形数据形成的半导体集成电路的光掩模的方法，包括以下步骤：根据预定的参考将半导体集成电路的绘制图案分类成多个等级并提取它们，并提取它们，确定检查精度并且根据所确定的检查精度是否满足来确定光掩模的质量。

8. 发明授权

US5130290A Water-sensitive coloring sheet 失效
标题翻译：水敏性着色片
公开(公告)号：US5130290A
公开(公告)日：1992-07-14
申请号：US497205
申请日：1990-03-22
申请人： Tadashi Tanimoto
发明人： Tadashi Tanimoto
IPC分类号： B41M3/00
CPC分类号： B41M3/001
摘要： Disclosed are a water-sensitive coloring sheet comprising:(a) a substrate and(b) a water-sensitive coloring layer containing a colorless or pale-colored basic dye, a color developing material capable of forming a color on contact with the dye, a densensitizer and a binder, and a method for forming colored image on such water-sensitive coloring sheet by application of water.
摘要翻译：公开了一种水敏性着色片，其包含：（a）基材和（b）含有无色或浅色碱性染料的水敏着色层，能够形成与染料接触的颜色的显色材料，浓缩敏化剂和粘合剂，以及通过施加水在这种水敏着色片上形成有色图像的方法。

9. 发明申请

US20070020880A1 Method of fabricating a semiconductor device and a method of generating a mask pattern 失效
标题翻译：制造半导体器件的方法和产生掩模图案的方法
公开(公告)号：US20070020880A1
公开(公告)日：2007-01-25
申请号：US11522995
申请日：2006-09-19
申请人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
发明人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , G06F17/5068 , H01L21/76229
摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.
摘要翻译：至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。在包括凹槽内部的半导体衬底的表面上形成绝缘膜。使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜形成在第二区域中。在这两种情况下，剩余的绝缘膜被抛光。

10. 发明授权

US07115478B2 Method of fabricating a semiconductor device and a method of generating a mask pattern 有权
标题翻译：制造半导体器件的方法和产生掩模图案的方法
公开(公告)号：US07115478B2
公开(公告)日：2006-10-03
申请号：US10663642
申请日：2003-09-17
申请人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
发明人： Kiyohito Mukai , Tadashi Tanimoto , Mitsumi Ito
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , G06F17/5068 , H01L21/76229
摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.
摘要翻译：至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。在包括凹槽内部的半导体衬底的表面上形成绝缘膜。使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜形成在第二区域中。在这两种情况下，剩余的绝缘膜被抛光。

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