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1. 发明授权

US06912559B1 System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit 有权
标题翻译：用于提高由浮点单元执行的平方根操作的准确性的系统和方法
公开(公告)号：US06912559B1
公开(公告)日：2005-06-28
申请号：US09363637
申请日：1999-07-30
申请人： Ying-wai Ho , Michael J. Schulte , John L. Kelley
发明人： Ying-wai Ho , Michael J. Schulte , John L. Kelley
IPC分类号： G06F7/38 , G06F7/487 , G06F5/552
CPC分类号： G06F7/4876
摘要： The accuracy of approximating the reciprocal and the reciprocal square root of a number (N) is improved. Approximating the reciprocal of N includes: (a) estimating the reciprocal of N to produce an estimate (Xi); (b) determining a first intermediate result (IR1) according to the equation: IR1=1−N*Xi; (c) multiplying IR1 by Xi to produce a second intermediate result (IR2); and (d) adding Xi to IR2 to produce an approximation of the reciprocal of N. Approximating the reciprocal square root includes: (a) estimating the reciprocal square root of N to produce Xi; (b) multiplying Xi by N to produce IR1; (c) determining IR2 according to the equation: IR2=(1−Xi*IR1)/2; (d) multiplying IR2 by Xi to produce a third intermediate result (IR3); and (e) adding IR3 to Xi to produce an approximation of the reciprocal square root of the number.
摘要翻译：改善了近似数（N）的倒数和倒数平方根的精度。近似N的倒数包括：（a）估计N的倒数以产生估计（X 1）; （b）根据以下等式确定第一中间结果（IR1）：IR1 = 1-N * XI1; （c）将IR1乘以X i i以产生第二中间结果（IR2）; 并且（d）向IR2添加XII以产生N的倒数的近似。近似平方根包括：（a）估计N的倒数平方根以产生X i （b）将X i i乘以N以产生IR1; （c）根据以下等式确定IR2：IR2 =（1-X1 * IR1）/ 2; （d）将IR2乘以XII i以产生第三中间结果（IR3）; 和（e）将IR3加入到XII中以产生该数的倒数平方根的近似值。

2. 发明授权

US06631392B1 Method and apparatus for predicting floating-point exceptions 有权
标题翻译：用于预测浮点异常的方法和装置
公开(公告)号：US06631392B1
公开(公告)日：2003-10-07
申请号：US09363638
申请日：1999-07-30
申请人： XingYu Jiang , Ying-wai Ho , John L. Kelley
发明人： XingYu Jiang , Ying-wai Ho , John L. Kelley
IPC分类号： G06F738
CPC分类号： G06F7/4991 , G06F7/483
摘要： A method and apparatus predict whether an overflow or underflow floating-point exception could occur as a result of a data processing system performing a particular floating-point operation. Predictions are made based on at least one overflow threshold value, at least first and second underflow threshold values, and a preliminary result exponent value derived from the values of the exponents of the floating-point numbers that are about to be acted upon. The preliminary result exponent is compared to an overflow or underflow threshold value in order to predict whether there is a possibility that an overflow or underflow floating-point exception could occur. Overflow and underflow exceptions are predicted and an exception prediction signal is generated. The exception prediction signals that are generated may be used by data processing system control units, for example, to temporarily halt any parallel processing operations that may be affected by an overflow or underflow floating-point exception.
摘要翻译：一种方法和装置预测作为执行特定浮点运算的数据处理系统的结果是否可能发生溢出或下溢浮点异常。基于至少一个溢出阈值，至少第一和第二下溢阈值以及从要被作用的浮点数的指数的值导出的初步结果指数值进行预测。将初步结果指数与溢出或下溢阈值进行比较，以便预测是否存在可能发生溢出或下溢浮点异常的可能性。预测溢出和下溢异常，并产生异常预测信号。生成的异常预测信号可以由数据处理系统控制单元使用，例如暂时停止可能受溢出或下溢浮点异常影响的任何并行处理操作。

3. 发明授权

US08024393B2 Processor with improved accuracy for multiply-add operations 有权
标题翻译：处理器具有提高的乘法运算精度
公开(公告)号：US08024393B2
公开(公告)日：2011-09-20
申请号：US11949418
申请日：2007-12-03
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

4. 发明授权

US07346643B1 Processor with improved accuracy for multiply-add operations 有权
标题翻译：处理器具有提高的乘法运算精度
公开(公告)号：US07346643B1
公开(公告)日：2008-03-18
申请号：US09364512
申请日：1999-07-30
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

5. 发明申请

US20080183791A1 Processor With Improved Accuracy For Multiply-Add Operations 有权
标题翻译：处理器具有改进的准确性以增加操作
公开(公告)号：US20080183791A1
公开(公告)日：2008-07-31
申请号：US11949418
申请日：2007-12-03
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

6. 发明授权

US5500943A Data processor with rename buffer and FIFO buffer for in-order instruction completion 失效
标题翻译：具有重命名缓冲器和FIFO缓冲器的数据处理器，用于按顺序指令完成
公开(公告)号：US5500943A
公开(公告)日：1996-03-19
申请号：US442913
申请日：1995-05-17
申请人： Ying-wai Ho , Bradley G. Burgess
发明人： Ying-wai Ho , Bradley G. Burgess
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/3863
摘要： A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled to the first calculation circuitry and stores a series of first results received from the first calculation circuitry. The rename buffer outputs the series of first results to a first predetermined register. The queue is also coupled to the first calculation circuitry and stores a series of second results. The queue outputs the sequence of second results to a second predetermined register in the same the sequence as it received the second results from the first calculation circuitry.
摘要翻译：数据处理器具有第一计算电路（26），重命名缓冲器（34）和队列（36）。第一计算电路从提供的操作数和接收的编程指令产生第一和第二结果。重命名缓冲器耦合到第一计算电路并存储从第一计算电路接收的一系列第一结果。重命名缓冲器将一系列第一结果输出到第一预定寄存器。队列还耦合到第一计算电路并存储一系列第二结果。队列以与从第一计算电路接收到第二结果的顺序相同的顺序将第二结果的序列输出到第二预定寄存器。

7. 发明授权

US07724261B2 Processor having a compare extension of an instruction set architecture 有权
标题翻译：具有指令集架构的比较扩展的处理器
公开(公告)号：US07724261B2
公开(公告)日：2010-05-25
申请号：US11806845
申请日：2007-06-04
申请人： Radhika Thekkath , G. Michael Uhler , Ying-wai Ho , Chandlee B. Harrell
发明人： Radhika Thekkath , G. Michael Uhler , Ying-wai Ho , Chandlee B. Harrell
IPC分类号： G06T1/20
CPC分类号： G06T15/005 , G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30025 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30112 , G06F9/3013 , G06F9/3885
摘要： A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.
摘要翻译：具有包含一组高性能浮点运算的指令集架构的比较扩展的处理器。指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。该扩展包括针对浮点数的幅度比较和一对32位固定点整数与配对单个浮点格式之间的转换的指令。

8. 发明申请

US20080022077A1 Processor having a compare extension of an instruction set architecture 有权
标题翻译：具有指令集架构的比较扩展的处理器
公开(公告)号：US20080022077A1
公开(公告)日：2008-01-24
申请号：US11806845
申请日：2007-06-04
申请人： Radhika Thekkath , G. Uhler , Ying-wai Ho , Chandlee Harrell
发明人： Radhika Thekkath , G. Uhler , Ying-wai Ho , Chandlee Harrell
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06T15/005 , G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30025 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30112 , G06F9/3013 , G06F9/3885
摘要： A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.
摘要翻译：具有包含一组高性能浮点运算的指令集架构的比较扩展的处理器。指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。该扩展包括针对浮点数的幅度比较和一对32位固定点整数与配对单个浮点格式之间的转换的指令。

9. 发明授权

US07242414B1 Processor having a compare extension of an instruction set architecture 有权
标题翻译：具有指令集架构的比较扩展的处理器
公开(公告)号：US07242414B1
公开(公告)日：2007-07-10
申请号：US09364786
申请日：1999-07-30
申请人： Radhika Thekkath , G. Michael Uhler , Ying-wai Ho , Chandlee B. Harrell
发明人： Radhika Thekkath , G. Michael Uhler , Ying-wai Ho , Chandlee B. Harrell
IPC分类号： G09G5/30
CPC分类号： G06T15/005 , G06F7/483 , G06F9/30014 , G06F9/30021 , G06F9/30025 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30112 , G06F9/3013 , G06F9/3885
摘要： A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to a magnitude compare of floating point numbers and conversions between a pair of 32-bit fixed point integers and paired-single floating point format.
摘要翻译：具有包含一组高性能浮点运算的指令集架构的比较扩展的处理器。指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。该扩展包括针对浮点数的幅度比较和一对32位固定点整数与配对单个浮点格式之间的转换的指令。

10. 发明授权

US06714197B1 Processor having an arithmetic extension of an instruction set architecture 有权
标题翻译：具有指令集架构的算术扩展的处理器
公开(公告)号：US06714197B1
公开(公告)日：2004-03-30
申请号：US09364787
申请日：1999-07-30
申请人： Radhika Thekkath , G. Michael Uhler , Ying-wai Ho , Chandlee B. Harrell
发明人： Radhika Thekkath , G. Michael Uhler , Ying-wai Ho , Chandlee B. Harrell
IPC分类号： G06T1520
CPC分类号： G06T15/00 , G06F9/30014 , G06F9/30025 , G06F9/345 , G06T15/20
摘要： A processor having an arithmetic extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to reduction add, reduction multiply, reciprocal, and reciprocal square root.
摘要翻译：具有包含一组高性能浮点运算的指令集架构的算术扩展的处理器。指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。该扩展包括针对减少添加，减少乘数，倒数和倒数平方根的指令。

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