专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06631392B1 Method and apparatus for predicting floating-point exceptions 有权
标题翻译：用于预测浮点异常的方法和装置
公开(公告)号：US06631392B1
公开(公告)日：2003-10-07
申请号：US09363638
申请日：1999-07-30
申请人： XingYu Jiang , Ying-wai Ho , John L. Kelley
发明人： XingYu Jiang , Ying-wai Ho , John L. Kelley
IPC分类号： G06F738
CPC分类号： G06F7/4991 , G06F7/483
摘要： A method and apparatus predict whether an overflow or underflow floating-point exception could occur as a result of a data processing system performing a particular floating-point operation. Predictions are made based on at least one overflow threshold value, at least first and second underflow threshold values, and a preliminary result exponent value derived from the values of the exponents of the floating-point numbers that are about to be acted upon. The preliminary result exponent is compared to an overflow or underflow threshold value in order to predict whether there is a possibility that an overflow or underflow floating-point exception could occur. Overflow and underflow exceptions are predicted and an exception prediction signal is generated. The exception prediction signals that are generated may be used by data processing system control units, for example, to temporarily halt any parallel processing operations that may be affected by an overflow or underflow floating-point exception.
摘要翻译：一种方法和装置预测作为执行特定浮点运算的数据处理系统的结果是否可能发生溢出或下溢浮点异常。基于至少一个溢出阈值，至少第一和第二下溢阈值以及从要被作用的浮点数的指数的值导出的初步结果指数值进行预测。将初步结果指数与溢出或下溢阈值进行比较，以便预测是否存在可能发生溢出或下溢浮点异常的可能性。预测溢出和下溢异常，并产生异常预测信号。生成的异常预测信号可以由数据处理系统控制单元使用，例如暂时停止可能受溢出或下溢浮点异常影响的任何并行处理操作。

2. 发明申请

US20080183791A1 Processor With Improved Accuracy For Multiply-Add Operations 有权
标题翻译：处理器具有改进的准确性以增加操作
公开(公告)号：US20080183791A1
公开(公告)日：2008-07-31
申请号：US11949418
申请日：2007-12-03
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

3. 发明授权

US08024393B2 Processor with improved accuracy for multiply-add operations 有权
标题翻译：处理器具有提高的乘法运算精度
公开(公告)号：US08024393B2
公开(公告)日：2011-09-20
申请号：US11949418
申请日：2007-12-03
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

4. 发明授权

US07346643B1 Processor with improved accuracy for multiply-add operations 有权
标题翻译：处理器具有提高的乘法运算精度
公开(公告)号：US07346643B1
公开(公告)日：2008-03-18
申请号：US09364512
申请日：1999-07-30
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

5. 发明授权

US06912559B1 System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit 有权
标题翻译：用于提高由浮点单元执行的平方根操作的准确性的系统和方法
公开(公告)号：US06912559B1
公开(公告)日：2005-06-28
申请号：US09363637
申请日：1999-07-30
申请人： Ying-wai Ho , Michael J. Schulte , John L. Kelley
发明人： Ying-wai Ho , Michael J. Schulte , John L. Kelley
IPC分类号： G06F7/38 , G06F7/487 , G06F5/552
CPC分类号： G06F7/4876
摘要： The accuracy of approximating the reciprocal and the reciprocal square root of a number (N) is improved. Approximating the reciprocal of N includes: (a) estimating the reciprocal of N to produce an estimate (Xi); (b) determining a first intermediate result (IR1) according to the equation: IR1=1−N*Xi; (c) multiplying IR1 by Xi to produce a second intermediate result (IR2); and (d) adding Xi to IR2 to produce an approximation of the reciprocal of N. Approximating the reciprocal square root includes: (a) estimating the reciprocal square root of N to produce Xi; (b) multiplying Xi by N to produce IR1; (c) determining IR2 according to the equation: IR2=(1−Xi*IR1)/2; (d) multiplying IR2 by Xi to produce a third intermediate result (IR3); and (e) adding IR3 to Xi to produce an approximation of the reciprocal square root of the number.
摘要翻译：改善了近似数（N）的倒数和倒数平方根的精度。近似N的倒数包括：（a）估计N的倒数以产生估计（X 1）; （b）根据以下等式确定第一中间结果（IR1）：IR1 = 1-N * XI1; （c）将IR1乘以X i i以产生第二中间结果（IR2）; 并且（d）向IR2添加XII以产生N的倒数的近似。近似平方根包括：（a）估计N的倒数平方根以产生X i （b）将X i i乘以N以产生IR1; （c）根据以下等式确定IR2：IR2 =（1-X1 * IR1）/ 2; （d）将IR2乘以XII i以产生第三中间结果（IR3）; 和（e）将IR3加入到XII中以产生该数的倒数平方根的近似值。

6. 发明授权

US4569446A Method and apparatus for feeding a product including fines 失效
标题翻译：用于喂食包括罚款的产品的方法和装置
公开(公告)号：US4569446A
公开(公告)日：1986-02-11
申请号：US437860
申请日：1982-10-29
申请人： John L. Kelley
发明人： John L. Kelley
IPC分类号： B07B1/46 , B07B13/04 , G01G13/04 , G01G13/08 , B07B13/05
CPC分类号： B07B1/4654 , B07B1/469 , B07B13/04 , G01G13/04 , G01G13/08 , Y10S209/92
摘要： This relates to a method of and an apparatus for feeding a product which includes fines to a weigh hopper. In lieu of the usual feeder pan, the last feeder pan in the feeder system is a duplex feeder pan including an upper feeding pan or level and a lower feeding pan or level. The upper feeder pan is provided with selected apertures therein so that fines will be separated from the remainder of the product and directed into the lower feeder pan. During the normal filling of the weigh hopper, both the upper feeder pan and the lower feeder pan will discharge into the weigh hopper. When a pre-selected underweight condition occurs, at least a part of the product from the upper pan will be diverted from immediately entering into the weigh hopper, while the feeding of the fines will continue so as to bring the weight of the product within the weigh hopper up to the pre-selected weight with a minimum of overweight.
摘要翻译：本发明涉及一种将包含细粉的产品进料到称重料斗的方法和设备。代替通常的进料盘，进料器系统中的最后一个进料盘是包括上进料盘或液位和下进料盘或液位的双面进料盘。上部进料盘在其中设置有选定的孔，使得细粒将与产品的其余部分分离并引导到下部进料盘中。在称重料斗正常填充期间，上饲料盘和下饲料盘两者都将排放到料斗中。当发生预先选择的重量不足的情况时，来自上锅的产品的至少一部分将被转入立即进入称重料斗，而细粉的供料将继续进行，以使产品的重量在称重料斗达到预先选定的重量，最小超重。

7. 发明授权

US07707389B2 Multi-ISA instruction fetch unit for a processor, and applications thereof 有权
标题翻译：用于处理器的多ISA指令获取单元及其应用
公开(公告)号：US07707389B2
公开(公告)日：2010-04-27
申请号：US10698061
申请日：2003-10-31
申请人： Soumya Banerjee , John L. Kelley , Ryan C. Kinter
发明人： Soumya Banerjee , John L. Kelley , Ryan C. Kinter
IPC分类号： G06F9/30
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/30174 , G06F9/30178
摘要： A method and apparatus for recoding one or more instruction sets. An expand instruction and an expandable instruction are read from an instruction cache. A tag compare and way selection unit checks to verify each instruction is a desired instruction. An instruction staging unit dispatches the expand instruction to a first recoder and the expandable instruction to a second recoder of a recoding unit. At least one information bit based on the expand instruction is generated at the first recoder. The second recoder uses the at least one information bit generated at the first recoder to recode the expandable instruction, and the recoded expandable instruction is placed in an instruction buffer.
摘要翻译：一种用于重新编码一个或多个指令集的方法和装置。从指令高速缓存中读取扩展指令和可扩展指令。标签比较和方式选择单元检查以验证每条指令是否是所需的指令。指令分段单元将扩展指令分派到第一重新编码器，并将扩展指令分配给编码单元的第二编码器。在第一记录器处产生基于扩展指令的至少一个信息位。第二记录器使用在第一记录器处生成的至少一个信息位对可扩展指令进行重新编码，并且重新编码的可扩展指令被放置在指令缓冲器中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式