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1. 发明授权

US06631392B1 Method and apparatus for predicting floating-point exceptions 有权
标题翻译：用于预测浮点异常的方法和装置
公开(公告)号：US06631392B1
公开(公告)日：2003-10-07
申请号：US09363638
申请日：1999-07-30
申请人： XingYu Jiang , Ying-wai Ho , John L. Kelley
发明人： XingYu Jiang , Ying-wai Ho , John L. Kelley
IPC分类号： G06F738
CPC分类号： G06F7/4991 , G06F7/483
摘要： A method and apparatus predict whether an overflow or underflow floating-point exception could occur as a result of a data processing system performing a particular floating-point operation. Predictions are made based on at least one overflow threshold value, at least first and second underflow threshold values, and a preliminary result exponent value derived from the values of the exponents of the floating-point numbers that are about to be acted upon. The preliminary result exponent is compared to an overflow or underflow threshold value in order to predict whether there is a possibility that an overflow or underflow floating-point exception could occur. Overflow and underflow exceptions are predicted and an exception prediction signal is generated. The exception prediction signals that are generated may be used by data processing system control units, for example, to temporarily halt any parallel processing operations that may be affected by an overflow or underflow floating-point exception.
摘要翻译：一种方法和装置预测作为执行特定浮点运算的数据处理系统的结果是否可能发生溢出或下溢浮点异常。基于至少一个溢出阈值，至少第一和第二下溢阈值以及从要被作用的浮点数的指数的值导出的初步结果指数值进行预测。将初步结果指数与溢出或下溢阈值进行比较，以便预测是否存在可能发生溢出或下溢浮点异常的可能性。预测溢出和下溢异常，并产生异常预测信号。生成的异常预测信号可以由数据处理系统控制单元使用，例如暂时停止可能受溢出或下溢浮点异常影响的任何并行处理操作。

2. 发明申请

US20080183791A1 Processor With Improved Accuracy For Multiply-Add Operations 有权
标题翻译：处理器具有改进的准确性以增加操作
公开(公告)号：US20080183791A1
公开(公告)日：2008-07-31
申请号：US11949418
申请日：2007-12-03
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

3. 发明授权

US08024393B2 Processor with improved accuracy for multiply-add operations 有权
标题翻译：处理器具有提高的乘法运算精度
公开(公告)号：US08024393B2
公开(公告)日：2011-09-20
申请号：US11949418
申请日：2007-12-03
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

4. 发明授权

US07346643B1 Processor with improved accuracy for multiply-add operations 有权
标题翻译：处理器具有提高的乘法运算精度
公开(公告)号：US07346643B1
公开(公告)日：2008-03-18
申请号：US09364512
申请日：1999-07-30
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

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