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1. 发明授权

US07378740B2 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US07378740B2
公开(公告)日：2008-05-27
申请号：US11196038
申请日：2005-08-02
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7681 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

2. 发明申请

US20050263876A1 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US20050263876A1
公开(公告)日：2005-12-01
申请号：US11196038
申请日：2005-08-02
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/768 , H01L23/12 , H01L23/532
CPC分类号： H01L21/7681 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

3. 发明授权

US06265780B1 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US06265780B1
公开(公告)日：2001-07-24
申请号：US09203035
申请日：1998-12-01
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L2348
CPC分类号： H01L21/76832 , H01L21/7681 , H01L21/76813 , H01L21/76835
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the dielectric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的介电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

4. 发明授权

US6025264A Fabricating method of a barrier layer 失效
标题翻译：阻挡层的制造方法
公开(公告)号：US6025264A
公开(公告)日：2000-02-15
申请号：US52608
申请日：1998-03-31
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun , Yimin Huang
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun , Yimin Huang
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L23/522 , H01L29/78
CPC分类号： H01L21/76843 , H01L23/5226 , H01L2924/0002
摘要： A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.
摘要翻译：一种用于形成阻挡层的方法，包括以下步骤：首先提供其上已经形成有导电层的半导体衬底。然后，在导电层和半导体衬底上沉积诸如有机低k电介质层的电介质层。接下来，形成在暴露导电层的电介质层中的开口。此后，第一阻挡层沉积到开口和周围区域中。第一阻挡层可以是通过等离子体增强化学气相沉积（PECVD）法，低压化学气相沉积法（LPCVD）法，电子束蒸发法或溅射法。最后，在第一阻挡层上形成第二阻挡层。第二阻挡层可以是钛/氮化钛（Ti / TiN）层，氮化钨（WN）层，钽（Ta）层或氮化钽（TaN）层。

5. 发明授权

US6020258A Method for unlanded via etching using etch stop 失效
标题翻译：使用蚀刻停止法进行无衬底通孔蚀刻的方法
公开(公告)号：US6020258A
公开(公告)日：2000-02-01
申请号：US982266
申请日：1997-12-01
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76834 , Y10S438/97
摘要： A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.
摘要翻译：形成多层互连结构，其方法是减少与无衬层通孔的形成和随后填充有关的问题。在层间电介质的表面上设置一级布线。第一级布线的上表面和侧壁被不同于用于将第一级布线与上层布线分开的金属间电介质的蚀刻停止材料覆盖。金属间电介质层沉积在第一层布线上，并通过金属间电介质蚀刻通孔，以使布线线上方的蚀刻停止材料露出，同时蚀刻停止材料上的通孔蚀刻停止。去除蚀刻停止材料以露出布线的上表面的一部分，并且在通孔内形成金属塞，然后形成与金属塞接触的上层布线。

6. 发明授权

US5960299A Method of fabricating a shallow-trench isolation structure in integrated circuit 失效
标题翻译：在集成电路中制造浅沟槽隔离结构的方法
公开(公告)号：US5960299A
公开(公告)日：1999-09-28
申请号：US181466
申请日：1998-10-28
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.
摘要翻译：提供了一种用于在集成电路中制造浅沟槽隔离（STI）结构的半导体制造方法，其可以防止在STI结构的氧化物塞中发生微细纹理，从而进一步防止桥接效应的发生，要通过STI结构电隔离的电路元件之间的电路。该方法的特征在于使用激光退火工艺来除去在用于去除氧化物层的上部以形成氧化物的化学机械抛光（CMP）工艺期间在氧化物塞的顶表面上形成的微观尺度堵塞该方法因此可以防止桥接效应的发生和由于形成在现有技术中将会出现的微纹理造成的短路。

7. 发明授权

US5801094A Dual damascene process 失效
标题翻译：双镶嵌工艺
公开(公告)号：US5801094A
公开(公告)日：1998-09-01
申请号：US873500
申请日：1997-06-12
申请人： Tri-Rung Yew , Meng-Chang Liu , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Meng-Chang Liu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/7681 , H01L21/76804
摘要： A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.
摘要翻译：双镶嵌工艺通过首先在器件结构上提供层间氧化物并用蚀刻停止层覆盖层间氧化物层，形成两层金属互连结构。蚀刻停止层被图案化以形成对应于将要形成在两层互连结构的第一层中的互连图案的开口。在蚀刻停止层被图案化之后，在蚀刻停止层上方提供金属间氧化物层。因为蚀刻停止层相对较薄，所以形成在金属间氧化物层的表面上的形貌相对较小。然后在金属间氧化物层之上提供光致抗蚀剂掩模，其中掩模中的开口在布线的图案中的金属间氧化物层的暴露部分中设置有互连结构的第二层。蚀刻金属间氧化物层，并且蚀刻工艺继续在层间氧化物中形成开口，其中层间氧化物被蚀刻停止层中的开口暴露。因此，在单个蚀刻步骤中，限定了用于二级布线和第一级互连的开口。然后将金属沉积在结构上，通过化学机械抛光除去多余的金属以限定两层互连结构。

8. 发明授权

US6153466A Method for increasing capacitance 失效
标题翻译：增加电容的方法
公开(公告)号：US6153466A
公开(公告)日：2000-11-28
申请号：US96349
申请日：1998-06-12
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/84
摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-SI on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.
摘要翻译：通过沉积掺杂多晶硅层来形成DRAM单元的电容器，图案化掺杂多晶硅层以限定电容器的下电极的范围，然后在层上沉积第一层半球状硅（HSG-Si）的掺杂多晶硅。 HSG-Si的第一层的生长被中断，然后生长第二层HSG-Si。在一个方面，HSG-Si的第一层的生长可以通过冷却沉积衬底或停止沉积一段时间而中断，然后重新开始沉积，以在电极的表面上提供第二层HSG-SI。如果重新开始的增长以独立于第一过程的方式发起，则第一层的增长中断，无论是通过冷却还是延迟，都是足够的; 即第二层HSG-Si独立生长。在本发明的另一方面，可以通过从沉积系统中去除电极并执行回蚀作业来中断第一层的生长。在回蚀作业之后，将电极重新引入沉积系统，并在蚀刻的表面上生长第二层HSG-Si。该纹理硅结构形成DRAM电容器的下电极。

9. 发明授权

US5976931A Method for increasing capacitance 失效
标题翻译：增加电容的方法
公开(公告)号：US5976931A
公开(公告)日：1999-11-02
申请号：US775813
申请日：1996-12-31
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/84
摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.
摘要翻译：通过沉积掺杂多晶硅层来形成DRAM单元的电容器，图案化掺杂多晶硅层以限定电容器的下电极的范围，然后在层上沉积第一层半球状硅（HSG-Si）的掺杂多晶硅。 HSG-Si的第一层的生长被中断，然后生长第二层HSG-Si。在一个方面，HSG-Si的第一层的生长可以通过冷却沉积衬底或停止沉积一段时间而中断，然后重新沉积以在电极的表面上提供第二层HSG-Si。如果重新开始的增长以独立于第一过程的方式发起，则第一层的增长中断，无论是通过冷却还是延迟，都是足够的; 即第二层HSG-Si独立生长。在本发明的另一方面，可以通过从沉积系统中去除电极并执行回蚀作业来中断第一层的生长。在回蚀作业之后，将电极重新引入沉积系统，并在蚀刻的表面上生长第二层HSG-Si。该纹理硅结构形成DRAM电容器的下电极。

10. 发明授权

US5869368A Method to increase capacitance 失效
标题翻译：增加电容的方法
公开(公告)号：US5869368A
公开(公告)日：1999-02-09
申请号：US934785
申请日：1997-09-22
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40 , H01L28/92
摘要： A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact with one source/drain region of a transfer FET. The lower capacitor electrode includes a first layer of polysilicon deposited over part of the transfer FET and in contact with the source/drain region of the transfer FET. An oxide layer is deposited over the first polysilicon layer and then a sparse layer of hemispherical grained polysilicon is deposited on the surface of the oxide layer. The sparse layer of hemispherical grained polysilicon has grains on the order of approximately 100 nanometers across that are separated on the average by approximately 100 nanometers. The layer of oxide is etched using the sparse grains of hemispherical grained polysilicon as a mask, with the etch process stopping on the surface of the first layer of polysilicon. A second layer of polysilicon is deposited over the remaining grains of hemispherical grained polysilicon and over the column-shaped portions of the oxide layer left by the etching stop. A capacitor dielectric is formed over the second layer of polysilicon and then an upper capacitor electrode is provided.
摘要翻译：用于DRAM的高电容电容存储电容器具有与转移FET的一个源极/漏极区域接触的下部电极。下部电容器电极包括沉积在转移FET的一部分上并与转移FET的源极/漏极区域接触的第一多晶硅层。在第一多晶硅层上沉积氧化物层，然后在氧化物层的表面上沉积半球状晶粒多晶硅的稀疏层。半球状粒状多晶硅的稀疏层具有约100纳米级的晶粒，平均分离约100纳米。使用半球状粒状多晶硅的稀疏晶粒作为掩模蚀刻氧化物层，其中蚀刻工艺停止在第一层多晶硅的表面上。第二层多晶硅沉积在半球状晶粒多晶硅的剩余晶粒之上，并在氧化物层的残留在蚀刻停止点的柱状部分之上。在第二多晶硅层上形成电容器电介质，然后提供上电容器电极。

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