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1. 发明授权

US07825522B2 Hybrid bump capacitor 有权
标题翻译：混合电容器
公开(公告)号：US07825522B2
公开(公告)日：2010-11-02
申请号：US11741195
申请日：2007-04-27
申请人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H01L23/48 , H01L27/108
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.
摘要翻译：公开了一种在芯片上制造的器件。该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，以及（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。

2. 发明授权

US08384226B2 Hybrid bump capacitor 失效
标题翻译：混合电容器
公开(公告)号：US08384226B2
公开(公告)日：2013-02-26
申请号：US12885722
申请日：2010-09-20
申请人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H01L23/48 , H01L27/108 , H01L21/00
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译：公开了一种在芯片上制造的器件。该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。第一图案和第二图案可以被成形为互锁梳。

3. 发明申请

US20130057325A1 AUTOMATIC FREQUENCY CALIBRATION OF A MULTI-LCVCO PHASE LOCKED LOOP WITH ADAPTIVE THRESHOLDS AND PROGRAMMABLE CENTER CONTROL VOLTAGE 失效
标题翻译：具有自适应阈值和可编程中心控制电压的多LCVCO相锁定环路的自动频率校准
公开(公告)号：US20130057325A1
公开(公告)日：2013-03-07
申请号：US13223418
申请日：2011-09-01
申请人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
发明人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
IPC分类号： H03L7/08 , H03L7/099
CPC分类号： H03L7/08
摘要： Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
摘要翻译：所描述的实施例提供了一种通过校准引擎校准具有一个或多个可调节振荡器的锁相环（PLL）的方法。该方法包括进入PLL的校准模式。 PLL被设置为初始状态，从而选择用于校准的可调振荡器之一，初始阈值窗口和所选择的可调振荡器的初始调谐频带。如果所选择的可调节振荡器的控制信号不在初始阈值窗口内，则校准引擎迭代地调整以下至少一个：（i）所选择的可调节振荡器的选定调谐带，（ii）所选择的可调振荡器和（ iii）所选择的阈值窗口，直到所选择的可调节振荡器的控制信号在调整的阈值窗口内。如果控制信号在阈值窗口内，PLL的一个或多个校准设置被存储并用于设置PLL操作。

4. 发明授权

US08432229B2 PVT consistent PLL incorporating multiple LCVCOs 失效
标题翻译： PVT一致的PLL结合了多个LCVCO
公开(公告)号：US08432229B2
公开(公告)日：2013-04-30
申请号：US13179653
申请日：2011-07-11
申请人： Yikui Jen Dong , Freeman Y. Zhong
发明人： Yikui Jen Dong , Freeman Y. Zhong
IPC分类号： H03B2201/025 , H03B2201/02
CPC分类号： H03L7/18 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/1265 , H03J2200/10 , H03L7/0891
摘要： In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL.
摘要翻译：在所描述的实施例中，宽调光范围（WTR）电感 - 电容（LC）锁相环（PLL）通过一组单独的LC压控振荡器（VCO）路径提供大范围的不同振荡频率。每个单独的宽范围LCVCO路径的输出被提供给多路复用器（MUX），其多路器（MUX）的输出是基于来自例如设备控制器的控制信号来选择的。单个宽范围LCVCO路径中的每一个包括将LCVCO耦合到电压调谐模块的环路滤波器的开关，其中当从MUX提供输出信号时，每个开关还接收控制信号以禁用或启用LCVCO路径。每个开关被配置为使得禁用时LCVCO吸收的漏电流最小化，并减少或消除每个休眠LCVCO的输入电容对PLL环路动态的影响。

5. 发明申请

US20120262238A1 PVT CONSISTENT PLL INCORPORATING MULTIPLE LCVCOS 失效
标题翻译： PVT一致性PLL包含多个LCVCOS
公开(公告)号：US20120262238A1
公开(公告)日：2012-10-18
申请号：US13179653
申请日：2011-07-11
申请人： Yikui Jen Dong , Freeman Y. Zhong
发明人： Yikui Jen Dong , Freeman Y. Zhong
IPC分类号： H03L7/08 , H03B5/08
CPC分类号： H03L7/18 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/1265 , H03J2200/10 , H03L7/0891
摘要： In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL.
摘要翻译：在所描述的实施例中，宽调光范围（WTR）电感 - 电容（LC）锁相环（PLL）通过一组单独的LC压控振荡器（VCO）路径提供大范围的不同振荡频率。每个单独的宽范围LCVCO路径的输出被提供给多路复用器（MUX），其多路器（MUX）的输出是基于来自例如设备控制器的控制信号来选择的。单个宽范围LCVCO路径中的每一个包括将LCVCO耦合到电压调谐模块的环路滤波器的开关，其中当从MUX提供输出信号时，每个开关还接收控制信号以禁用或启用LCVCO路径。每个开关被配置为使得禁用时LCVCO吸收的漏电流最小化，并减少或消除每个休眠LCVCO的输入电容对PLL环路动态的影响。

6. 发明授权

US08508308B2 Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage 失效
标题翻译：具有自适应阈值和可编程中心控制电压的多LCVCO锁相环的自动频率校准
公开(公告)号：US08508308B2
公开(公告)日：2013-08-13
申请号：US13223418
申请日：2011-09-01
申请人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
发明人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
IPC分类号： H03L7/085
CPC分类号： H03L7/08
摘要： Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
摘要翻译：所描述的实施例提供了一种通过校准引擎校准具有一个或多个可调节振荡器的锁相环（PLL）的方法。该方法包括进入PLL的校准模式。 PLL被设置为初始状态，从而选择用于校准的可调振荡器之一，初始阈值窗口和所选择的可调振荡器的初始调谐频带。如果所选择的可调节振荡器的控制信号不在初始阈值窗口内，则校准引擎迭代地调整以下至少一个：（i）所选择的可调节振荡器的选定调谐带，（ii）所选择的可调振荡器和（ iii）所选择的阈值窗口，直到所选择的可调节振荡器的控制信号在调整的阈值窗口内。如果控制信号在阈值窗口内，PLL的一个或多个校准设置被存储并用于设置PLL操作。

7. 发明申请

US20110006395A1 HYBRID BUMP CAPACITOR 失效
标题翻译：混合电容器
公开(公告)号：US20110006395A1
公开(公告)日：2011-01-13
申请号：US12885722
申请日：2010-09-20
申请人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译：公开了一种在芯片上制造的器件。该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。第一图案和第二图案可以被成形为互锁梳。

8. 发明申请

US20080018419A1 HYBRID BUMP CAPACITOR 有权
标题翻译：混合电容器
公开(公告)号：US20080018419A1
公开(公告)日：2008-01-24
申请号：US11741195
申请日：2007-04-27
申请人： Yikui Jen Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui Jen Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H03H7/00 , H01L21/62
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.
摘要翻译：公开了一种在芯片上制造的器件。器件通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，以及（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。

9. 发明授权

US08649476B2 Adjusting sampling phase in a baud-rate CDR using timing skew 有权
标题翻译：使用定时偏移调整波特率CDR中的采样相位
公开(公告)号：US08649476B2
公开(公告)日：2014-02-11
申请号：US13081651
申请日：2011-04-07
申请人： Amaresh Malipatil , Wingfaat Liu , Ye Liu , Freeman Y. Zhong , Chintan Desai
发明人： Amaresh Malipatil , Wingfaat Liu , Ye Liu , Freeman Y. Zhong , Chintan Desai
IPC分类号： H04B1/38
CPC分类号： H04L7/0062 , H04L25/03057 , H04L25/03343
摘要： In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.
摘要翻译：在所描述的实施例中，收发器包括具有眼睛取样器的波特率时钟和数据恢复（CDR）模块，以及用于自适应地设置诸如定时，均衡器和增益元件的各种电路元件的参数的适配模块。 CDR模块的数据采样时钟相位被设置为在例如由眼睛采样器检测到的数据眼睛的中心附近进行采样，并且数据错误采样锁存器的相位相对于CDR模块偏移数据采样锁存器的相位。由于驱动定时自适应的误差信号包含CDR模块所遇到的脉冲响应的信息，所以基于维持输入脉冲响应残差预测的相对等价，CDR模块的定时误差采样锁存器的相位是偏斜的，光标和剩余后光标相对于定时误差采样时钟相位。

10. 发明申请

US20120257652A1 ADJUSTING SAMPLING PHASE IN A BAUD-RATE CDR USING TIMING SKEW 有权
标题翻译：使用时间轴调整在波特率CDR中的采样相位
公开(公告)号：US20120257652A1
公开(公告)日：2012-10-11
申请号：US13081651
申请日：2011-04-07
申请人： Amaresh Malipatil , Wingfaat Liu , Ye Liu , Freeman Y. Zhong , Chintan Desai
发明人： Amaresh Malipatil , Wingfaat Liu , Ye Liu , Freeman Y. Zhong , Chintan Desai
IPC分类号： H04L7/08 , H04B1/38 , H03H7/30
CPC分类号： H04L7/0062 , H04L25/03057 , H04L25/03343
摘要： In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.
摘要翻译：在所描述的实施例中，收发器包括具有眼睛采样器的波特率时钟和数据恢复（CDR）模块，以及用于自适应地设置诸如定时，均衡器和增益元件的各种电路元件的参数的适配模块。 CDR模块的数据采样时钟相位被设置为在例如由眼睛采样器检测到的数据眼睛的中心附近进行采样，并且数据错误采样锁存器的相位相对于CDR模块偏移数据采样锁存器的相位。由于驱动定时自适应的误差信号包含CDR模块所遇到的脉冲响应的信息，所以基于维持输入脉冲响应残差预测的相对等价，CDR模块的定时误差采样锁存器的相位是偏斜的，光标和剩余后光标相对于定时误差采样时钟相位。

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