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1. 发明授权

US08649476B2 Adjusting sampling phase in a baud-rate CDR using timing skew 有权
标题翻译：使用定时偏移调整波特率CDR中的采样相位
公开(公告)号：US08649476B2
公开(公告)日：2014-02-11
申请号：US13081651
申请日：2011-04-07
申请人： Amaresh Malipatil , Wingfaat Liu , Ye Liu , Freeman Y. Zhong , Chintan Desai
发明人： Amaresh Malipatil , Wingfaat Liu , Ye Liu , Freeman Y. Zhong , Chintan Desai
IPC分类号： H04B1/38
CPC分类号： H04L7/0062 , H04L25/03057 , H04L25/03343
摘要： In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.
摘要翻译：在所描述的实施例中，收发器包括具有眼睛取样器的波特率时钟和数据恢复（CDR）模块，以及用于自适应地设置诸如定时，均衡器和增益元件的各种电路元件的参数的适配模块。 CDR模块的数据采样时钟相位被设置为在例如由眼睛采样器检测到的数据眼睛的中心附近进行采样，并且数据错误采样锁存器的相位相对于CDR模块偏移数据采样锁存器的相位。由于驱动定时自适应的误差信号包含CDR模块所遇到的脉冲响应的信息，所以基于维持输入脉冲响应残差预测的相对等价，CDR模块的定时误差采样锁存器的相位是偏斜的，光标和剩余后光标相对于定时误差采样时钟相位。

2. 发明申请

US20120257652A1 ADJUSTING SAMPLING PHASE IN A BAUD-RATE CDR USING TIMING SKEW 有权
标题翻译：使用时间轴调整在波特率CDR中的采样相位
公开(公告)号：US20120257652A1
公开(公告)日：2012-10-11
申请号：US13081651
申请日：2011-04-07
申请人： Amaresh Malipatil , Wingfaat Liu , Ye Liu , Freeman Y. Zhong , Chintan Desai
发明人： Amaresh Malipatil , Wingfaat Liu , Ye Liu , Freeman Y. Zhong , Chintan Desai
IPC分类号： H04L7/08 , H04B1/38 , H03H7/30
CPC分类号： H04L7/0062 , H04L25/03057 , H04L25/03343
摘要： In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.
摘要翻译：在所描述的实施例中，收发器包括具有眼睛采样器的波特率时钟和数据恢复（CDR）模块，以及用于自适应地设置诸如定时，均衡器和增益元件的各种电路元件的参数的适配模块。 CDR模块的数据采样时钟相位被设置为在例如由眼睛采样器检测到的数据眼睛的中心附近进行采样，并且数据错误采样锁存器的相位相对于CDR模块偏移数据采样锁存器的相位。由于驱动定时自适应的误差信号包含CDR模块所遇到的脉冲响应的信息，所以基于维持输入脉冲响应残差预测的相对等价，CDR模块的定时误差采样锁存器的相位是偏斜的，光标和剩余后光标相对于定时误差采样时钟相位。

3. 发明申请

US20060093028A1 Serial data link using decision feedback equalization 失效
标题翻译：使用判决反馈均衡的串行数据链路
公开(公告)号：US20060093028A1
公开(公告)日：2006-05-04
申请号：US10978755
申请日：2004-11-01
申请人： Vishnu Balan , Joseph Caroselli , Ye Liu , Chintan Desai , Jenn-Gang Chern
发明人： Vishnu Balan , Joseph Caroselli , Ye Liu , Chintan Desai , Jenn-Gang Chern
IPC分类号： H03H7/30
CPC分类号： H04L25/03343 , H04L2025/0349
摘要： A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.
摘要翻译：多相自适应判决反馈均衡器基于数据通信系统中的后续数据位的值来最小化当前数据位中的后标记符号间干扰。在一种形式中，接收机包括多个模块，每个模块具有相应的自适应判决反馈均衡器。响应于来自多个模块中的每一个的输出信号的处理器产生多个系数值。自适应判决反馈均衡器具有接收来自模块之一的相应输出信号的多个抽头和相应的系数值以产生相应的校正信号。校正信号与数据信号相加并被处理以恢复数据。系数的预先计算允许快速选择数据。多相操作允许更高的数据频率。

4. 发明授权

US06288656B1 Receive deserializer for regenerating parallel data serially transmitted over multiple channels 有权
标题翻译：接收解串器，用于重新生成多个通道串行传输的并行数据
公开(公告)号：US06288656B1
公开(公告)日：2001-09-11
申请号：US09469730
申请日：1999-12-21
申请人： Chintan Desai
发明人： Chintan Desai
IPC分类号： H03M900
CPC分类号： H04L25/14 , H04J3/0685 , H04L7/02 , H04L7/041
摘要： A receive deserializer which regenerates parellel data words that have been broken into smaller data words and serially transmitted over multiple data channels uses an external state machine to shift word clocks with respect to data until the output of the channel last to receive a predefined data reference pattern is framed and provides storage to hold data for the channels which receive the reference pattern earlier.
摘要翻译：一种接收解串器，其重新生成被分解成更小的数据字并且通过多个数据信道串行发送的连续数据字，使用外部状态机来相对于数据移动字时钟，直到信道的输出最后接收预定义的数据参考模式被构造并提供存储以保存用于更早接收参考模式的通道的数据。

5. 发明授权

US06862296B1 Receive deserializer circuit for framing parallel data 有权
标题翻译：接收并行电路用于构成并行数据
公开(公告)号：US06862296B1
公开(公告)日：2005-03-01
申请号：US09468746
申请日：1999-12-21
申请人： Chintan Desai
发明人： Chintan Desai
IPC分类号： H04J3/06 , H04L7/04
CPC分类号： H04L7/042 , H04J3/0685
摘要： A receive deserializer circuit which frames parallel data utilizes a skip-bit technique for aligning a predefined data reference pattern with a word clock. The receive deserializer circuit includes a sampling flip flop which receives serial data including a data reference pattern. The sampling flip flop samples and retimes the serial data to a recovered clock. A demultiplexer then deserializes the retimed serial data into a parallel data word which is timed to a word clock from a clock generator. A comparator makes comparisons of the parallel data word with a preset data reference pattern until a match results. A logic controller interprets whether the output of the comparator is a match and generates a shift pulse following each comparison which does not result in a match. The clock generator divides the recovered clock into eight phase clocks. One of the phase clocks is a word clock. Each time the clock generator receives a shift pulse from the logic controller, it disables all the phase clocks by one bit period. This results in a one is bit shift in all the clocks and a one bit shift in the parallel data generated on word clock each time there is no match from the comparator. When a match occurs, no shift pulse is generated by the logic controller, and the predefined data reference pattern and subsequent data words received on word clock are properly framed.
摘要翻译：帧并行数据的接收解串器电路利用跳跃比特技术将预定义的数据参考模式与字时钟对准。接收解串器电路包括采样触发器，其接收包括数据参考模式的串行数据。采样触发器采样并将串行数据重新定时到恢复的时钟。然后解复用器将重新定时的串行数据反序列化成并行数据字，其被定时到来自时钟发生器的字时钟。比较器将并行数据字与预设的数据参考模式进行比较，直到匹配结果。逻辑控制器解释比较器的输出是否匹配，并且在每个比较之后生成不产生匹配的移位脉冲。时钟发生器将恢复的时钟分为八个相位时钟。其中一个相位时钟是一个字时钟。每当时钟发生器从逻辑控制器接收到移位脉冲时，它将所有相位时钟禁止一个位周期。这导致一个是所有时钟中的位移位，并且每次与比较器不匹配时，在字时钟上产生的并行数据中的一位移位。当匹配发生时，逻辑控制器不产生移位脉冲，并且在字时钟上接收的预定义数据参考模式和后续数据字被正确地框架化。

6. 发明授权

US06265924B1 Non-uniform delay stages to increase the operating frequency range of delay lines 有权
标题翻译：不均匀的延迟级延长延时线的工作频率范围
公开(公告)号：US06265924B1
公开(公告)日：2001-07-24
申请号：US09468711
申请日：1999-12-21
申请人： Chintan Desai
发明人： Chintan Desai
IPC分类号： H03K513
CPC分类号： H03K5/131 , H03K5/133
摘要： A delay line provides a variable delay in the clock path and increases the operating frequency range through the use of delay stages which have non-uniform propagation delay with respect to one another. The range of operating frequency is increased by keeping the delay stages with the minimum propagation delay in the center of the delay line while the delay stages with the maximum propagation delay are toward the ends of the delay line.
摘要翻译：延迟线在时钟路径中提供可变延迟并且通过使用相对于彼此具有不均匀传播延迟的延迟级来增加工作频率范围。通过在延迟线的中心保持具有最小传播延迟的延迟级来增加工作频率的范围，而具有最大传播延迟的延迟级朝向延迟线的端部。

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