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1. 发明授权

US07961817B2 AC coupling circuit integrated with receiver with hybrid stable common-mode voltage generation and baseline wander compensation 失效
标题翻译：交流耦合电路与接收器集成，具有混合稳定的共模电压产生和基线漂移补偿
公开(公告)号：US07961817B2
公开(公告)日：2011-06-14
申请号：US11634671
申请日：2006-12-06
申请人： Yikui (Jen) Dong , Cathy Ye Liu , Freeman Yingquan Zhong , Shao Ming Hsu
发明人： Yikui (Jen) Dong , Cathy Ye Liu , Freeman Yingquan Zhong , Shao Ming Hsu
IPC分类号： H04L25/06 , H04L25/10
CPC分类号： H04L25/0276 , H04L25/06
摘要： In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.
摘要翻译：在接收机中，AC耦合解决方案使用完全集成电路，同时提供基线漂移补偿和共模电压生成。有用的是，在接收器输入引脚和输入缓冲器之间放置一个集成的电容器，并且高电阻阻抗元件连接到电容器之后的内部高速数据节点。片上电压产生和校正电路连接到阻抗元件的另一侧以产生共模电压，并为接收的数据电压电平提供动态的微调。电压校正电路由接收机的时钟和数据恢复单元（CDRU）检测到的数据的反馈来控制。反馈数据通过加权元件，其中反馈增益的量可调，以提供求和权重，从而实现所需的BLW补偿。寄存器位用于控制片上参考电压发生器，该发生器由电阻梯形成，用于产生参考电压。

2. 发明授权

US07825522B2 Hybrid bump capacitor 有权
标题翻译：混合电容器
公开(公告)号：US07825522B2
公开(公告)日：2010-11-02
申请号：US11741195
申请日：2007-04-27
申请人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H01L23/48 , H01L27/108
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.
摘要翻译：公开了一种在芯片上制造的器件。该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，以及（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。

3. 发明授权

US08384226B2 Hybrid bump capacitor 失效
标题翻译：混合电容器
公开(公告)号：US08384226B2
公开(公告)日：2013-02-26
申请号：US12885722
申请日：2010-09-20
申请人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H01L23/48 , H01L27/108 , H01L21/00
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译：公开了一种在芯片上制造的器件。该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。第一图案和第二图案可以被成形为互锁梳。

4. 发明申请

US20080063091A1 AC coupling circuit integrated with receiver with hybrid stable common-mode voltage generation and baseline-wander compensation 失效
标题翻译：交流耦合电路与接收器集成，具有混合稳定的共模电压产生和基线漂移补偿
公开(公告)号：US20080063091A1
公开(公告)日：2008-03-13
申请号：US11634671
申请日：2006-12-06
申请人： Yikui (Jen) Dong , Cathy Ye Liu , Freeman Yingquan Zhong , Shao Ming Hsu
发明人： Yikui (Jen) Dong , Cathy Ye Liu , Freeman Yingquan Zhong , Shao Ming Hsu
IPC分类号： H04L25/00
CPC分类号： H04L25/0276 , H04L25/06
摘要： In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.
摘要翻译：在接收机中，AC耦合解决方案使用完全集成电路，同时提供基线漂移补偿和共模电压生成。有用的是，在接收器输入引脚和输入缓冲器之间放置一个集成的电容器，并且高电阻阻抗元件连接到电容器之后的内部高速数据节点。片上电压产生和校正电路连接到阻抗元件的另一侧以产生共模电压，并为接收的数据电压电平提供动态的微调。电压校正电路由接收机的时钟和数据恢复单元（CDRU）检测到的数据的反馈来控制。反馈数据通过加权元件，其中反馈增益的量可调，以提供求和权重，从而实现所需的BLW补偿。寄存器位用于控制片上参考电压发生器，该发生器由电阻梯形成，用于产生参考电压。

5. 发明授权

US08432229B2 PVT consistent PLL incorporating multiple LCVCOs 失效
标题翻译： PVT一致的PLL结合了多个LCVCO
公开(公告)号：US08432229B2
公开(公告)日：2013-04-30
申请号：US13179653
申请日：2011-07-11
申请人： Yikui Jen Dong , Freeman Y. Zhong
发明人： Yikui Jen Dong , Freeman Y. Zhong
IPC分类号： H03B2201/025 , H03B2201/02
CPC分类号： H03L7/18 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/1265 , H03J2200/10 , H03L7/0891
摘要： In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL.
摘要翻译：在所描述的实施例中，宽调光范围（WTR）电感 - 电容（LC）锁相环（PLL）通过一组单独的LC压控振荡器（VCO）路径提供大范围的不同振荡频率。每个单独的宽范围LCVCO路径的输出被提供给多路复用器（MUX），其多路器（MUX）的输出是基于来自例如设备控制器的控制信号来选择的。单个宽范围LCVCO路径中的每一个包括将LCVCO耦合到电压调谐模块的环路滤波器的开关，其中当从MUX提供输出信号时，每个开关还接收控制信号以禁用或启用LCVCO路径。每个开关被配置为使得禁用时LCVCO吸收的漏电流最小化，并减少或消除每个休眠LCVCO的输入电容对PLL环路动态的影响。

6. 发明申请

US20120262238A1 PVT CONSISTENT PLL INCORPORATING MULTIPLE LCVCOS 失效
标题翻译： PVT一致性PLL包含多个LCVCOS
公开(公告)号：US20120262238A1
公开(公告)日：2012-10-18
申请号：US13179653
申请日：2011-07-11
申请人： Yikui Jen Dong , Freeman Y. Zhong
发明人： Yikui Jen Dong , Freeman Y. Zhong
IPC分类号： H03L7/08 , H03B5/08
CPC分类号： H03L7/18 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/1265 , H03J2200/10 , H03L7/0891
摘要： In described embodiments, a wide toning-range (WTR) inductive-capacitive (LC) phase locked loop (PLL) provides for a large range of differing oscillation frequencies with a set of individual LC voltage controlled oscillator (VCO) paths. The output of each individual wide range LCVCO path is provided to a multiplexor (MUX), whose output is selected based on a control signal from, for example, a device controller. Each of the set of individual wide range LCVCO paths includes a switch that couples the LCVCO to a loop filter of a voltage tuning module, wherein each switch also receives the control signal to disable or enable the LCVCO path when providing the output signal from the MUX. Each switch is configured so as to minimize leakage current drawn by the LCVCO when disabled, and to reduce or eliminate effects of input capacitance of each dormant LCVCO to the loop dynamics of the PLL.
摘要翻译：在所描述的实施例中，宽调光范围（WTR）电感 - 电容（LC）锁相环（PLL）通过一组单独的LC压控振荡器（VCO）路径提供大范围的不同振荡频率。每个单独的宽范围LCVCO路径的输出被提供给多路复用器（MUX），其多路器（MUX）的输出是基于来自例如设备控制器的控制信号来选择的。单个宽范围LCVCO路径中的每一个包括将LCVCO耦合到电压调谐模块的环路滤波器的开关，其中当从MUX提供输出信号时，每个开关还接收控制信号以禁用或启用LCVCO路径。每个开关被配置为使得禁用时LCVCO吸收的漏电流最小化，并减少或消除每个休眠LCVCO的输入电容对PLL环路动态的影响。

7. 发明授权

US09014252B2 Band-pass high-order analog filter backed hybrid receiver equalization 有权
标题翻译：带通高阶模拟滤波器支持的混合接收机均衡
公开(公告)号：US09014252B2
公开(公告)日：2015-04-21
申请号：US11634645
申请日：2006-12-06
申请人： Yikui (Jen) Dong , Cathy Ye Liu , Freeman Yingquan Zhong
发明人： Yikui (Jen) Dong , Cathy Ye Liu , Freeman Yingquan Zhong
IPC分类号： H03K5/159 , H03K5/01 , H04B1/10 , H04L25/03
CPC分类号： H04L25/03178 , H04L25/03057 , H04L2025/03356
摘要： A channel equalization scheme is provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid receiver equalizer. The hybrid receiver equalizer controls crosstalk while maintaining signal bandwidth and linearity of a signal by the high-order high frequency roll-off of the linear equalizer used. Using this configuration, the hybrid receiver equalizer eliminates the need for adaptive bandwidth controller used in conventional low-pass receiver equalization schemes. The hybrid receiver equalizer can be used in receivers for dual-speed simultaneous transmission on the same physical link. The hybrid receiver equalizer can also be used in receivers for simultaneous forward and back-channel transmission using differential-signaling in multi-Gbps transceivers.
摘要翻译：提供了一种信道均衡方案。使用连续时间线性均衡的线性均衡器和使用离散时间判决反馈均衡的判决反馈均衡器从混合接收机均衡器集成在一起。使用联合自适应算法来混合连续时间线性均衡方案和离散时间决策反馈均衡方案，以在混合接收机均衡器中形成符号间干扰消除的均衡方案。混合接收机均衡器控制串扰，同时通过所使用的线性均衡器的高阶高频滚降来维持信号的信号带宽和线性度。使用这种配置，混合接收机均衡器消除了对传统低通接收机均衡方案中使用的自适应带宽控制器的需要。混合接收均衡器可用于同一物理链路上双速同时传输的接收机。混合接收机均衡器也可以用于接收机，用于使用多Gbps收发器中的差分信号进行同步正向和反向信道传输。

8. 发明授权

US08520348B2 High-swing differential driver using low-voltage transistors 有权
标题翻译：高摆幅差动驱动器采用低压晶体管
公开(公告)号：US08520348B2
公开(公告)日：2013-08-27
申请号：US13335056
申请日：2011-12-22
申请人： Yikui Jen Dong
发明人： Yikui Jen Dong
IPC分类号： H03K17/16
CPC分类号： G06F13/4086
摘要： A differential line driver with N-paralleled slices for driving an impedance-matched transmission line. Each driver slice is a modified H-bridge driver using low-voltage, high-speed transistors. By using a voltage-dropping first resistor in each slice, a high-voltage power supply that would normally damage the transistors can be used to power the driver and produce a differential output signal with peak-to-peak amplitudes that otherwise might not be possible. Each transistor in each driver slice has a resistor disposed between the transistor and the respective output node of the driver to enhance ESD protection of the transistors and, in combination with the first resistor, to impedance match the driver to the transmission line.
摘要翻译：具有N平行片的差分线路驱动器，用于驱动阻抗匹配传输线。每个驱动器片是使用低电压，高速晶体管的修改后的H桥驱动器。通过在每个片中使用降压第一电阻，可以使用通常会损坏晶体管的高压电源为驱动器供电，并产生具有峰 - 峰幅度的差分输出信号，否则可能无法实现。每个驱动器片中的每个晶体管具有设置在晶体管和驱动器的相应输出节点之间的电阻器，以增强晶体管的ESD保护，并与第一电阻器组合以使驱动器与传输线路匹配。

9. 发明申请

US20130057325A1 AUTOMATIC FREQUENCY CALIBRATION OF A MULTI-LCVCO PHASE LOCKED LOOP WITH ADAPTIVE THRESHOLDS AND PROGRAMMABLE CENTER CONTROL VOLTAGE 失效
标题翻译：具有自适应阈值和可编程中心控制电压的多LCVCO相锁定环路的自动频率校准
公开(公告)号：US20130057325A1
公开(公告)日：2013-03-07
申请号：US13223418
申请日：2011-09-01
申请人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
发明人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
IPC分类号： H03L7/08 , H03L7/099
CPC分类号： H03L7/08
摘要： Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
摘要翻译：所描述的实施例提供了一种通过校准引擎校准具有一个或多个可调节振荡器的锁相环（PLL）的方法。该方法包括进入PLL的校准模式。 PLL被设置为初始状态，从而选择用于校准的可调振荡器之一，初始阈值窗口和所选择的可调振荡器的初始调谐频带。如果所选择的可调节振荡器的控制信号不在初始阈值窗口内，则校准引擎迭代地调整以下至少一个：（i）所选择的可调节振荡器的选定调谐带，（ii）所选择的可调振荡器和（ iii）所选择的阈值窗口，直到所选择的可调节振荡器的控制信号在调整的阈值窗口内。如果控制信号在阈值窗口内，PLL的一个或多个校准设置被存储并用于设置PLL操作。

10. 发明授权

US08508308B2 Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage 失效
标题翻译：具有自适应阈值和可编程中心控制电压的多LCVCO锁相环的自动频率校准
公开(公告)号：US08508308B2
公开(公告)日：2013-08-13
申请号：US13223418
申请日：2011-09-01
申请人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
发明人： Yikui Jen Dong , Freeman Y. Zhong , Tai Jing , Chaitanya Palusa
IPC分类号： H03L7/085
CPC分类号： H03L7/08
摘要： Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
摘要翻译：所描述的实施例提供了一种通过校准引擎校准具有一个或多个可调节振荡器的锁相环（PLL）的方法。该方法包括进入PLL的校准模式。 PLL被设置为初始状态，从而选择用于校准的可调振荡器之一，初始阈值窗口和所选择的可调振荡器的初始调谐频带。如果所选择的可调节振荡器的控制信号不在初始阈值窗口内，则校准引擎迭代地调整以下至少一个：（i）所选择的可调节振荡器的选定调谐带，（ii）所选择的可调振荡器和（ iii）所选择的阈值窗口，直到所选择的可调节振荡器的控制信号在调整的阈值窗口内。如果控制信号在阈值窗口内，PLL的一个或多个校准设置被存储并用于设置PLL操作。

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