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1. 发明授权

US06703317B1 Method to neutralize charge imbalance following a wafer cleaning process 失效
标题翻译：中和晶圆清洗过程后电荷不平衡的方法
公开(公告)号：US06703317B1
公开(公告)日：2004-03-09
申请号：US10356248
申请日：2003-01-30
申请人： Yi-Lung Cheng , Ming-Hwa Yoo , Sze-An Wu , Ying-Lung Wang
发明人： Yi-Lung Cheng , Ming-Hwa Yoo , Sze-An Wu , Ying-Lung Wang
IPC分类号： H01L21302
CPC分类号： H01L21/3105 , H01L21/02052 , H01L21/76826 , H01L21/76837 , Y10S438/906
摘要： A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.
摘要翻译：一种减少晶片工艺表面上的电荷不平衡的方法，包括提供具有包括最上面的第一材料层的工艺表面的半导体晶片; 根据包括喷射和洗涤中的至少一种的晶片清洁过程清洁工艺表面以在工艺表面产生电荷不平衡; 并且使所述工艺表面进行含氮等离子体处理以至少部分地中和所述电荷不平衡。

2. 发明申请

US20050153537A1 Novel nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure 有权
标题翻译：新型氮化物阻挡层，以防止双镶嵌结构中的金属（Cu）泄漏问题
公开(公告)号：US20050153537A1
公开(公告)日：2005-07-14
申请号：US10753637
申请日：2004-01-08
申请人： Yi-Lung Cheng , Ying-Lung Wang
发明人： Yi-Lung Cheng , Ying-Lung Wang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76826
摘要： A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.
摘要翻译：公开了一种用于形成复合阻挡层的方法，该复合阻挡层也用作镶嵌工艺中的蚀刻停止。将SiC层沉积在CVD处理室中的衬底上，随后沉积氮化硅层以完成复合势垒层。 SiC层对衬底中的铜层表现出优异的粘附性，并且通过避免反应性Si + 4+物质并由此防止CuSi X X形成的方法形成。氮化硅层的厚度足以为金属离子提供优异的阻挡能力，但保持尽可能的薄，以使复合阻挡层的介电常数最小化。复合阻挡层在氧化灰化步骤期间提供优异的铜氧化性能，并且与使用常规氮化硅阻挡层相比，能够以较低的漏电流制造铜层。

3. 发明申请

US20050121751A1 Carbon and halogen doped silicate glass dielectric layer and method for fabricating the same 失效
公开(公告)号：US20050121751A1
公开(公告)日：2005-06-09
申请号：US10729217
申请日：2003-12-04
申请人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
发明人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
IPC分类号： H01L21/31 , H01L21/316 , H01L21/76 , H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , C23C16/401 , H01L21/02126 , H01L21/02131 , H01L21/02211 , H01L21/02274 , H01L21/31629 , H01L21/31633 , H01L21/76802 , H01L21/76807 , H01L21/76835 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

4. 发明授权

US07296532B2 Bypass gas feed system and method to improve reactant gas flow and film deposition 有权
标题翻译：旁路气体进料系统和改善反应气流和薄膜沉积的方法
公开(公告)号：US07296532B2
公开(公告)日：2007-11-20
申请号：US10323950
申请日：2002-12-18
申请人： Yi-Lung Cheng , Mo-Chen Liao , Eric Tsai , Sze-Au Wu , Ying-Lung Wang
发明人： Yi-Lung Cheng , Mo-Chen Liao , Eric Tsai , Sze-Au Wu , Ying-Lung Wang
IPC分类号： C23C16/00
CPC分类号： C23C16/45561 , C23C16/4412 , C23C16/455 , C23C16/509
摘要： A method and reactant gas bypass system for carrying out a plasma enhanced chemical vapor deposition (PECVD) process with improved gas flow stability to avoid unionized reactant precursors and thickness non-uniformities the method including providing a semiconductor process wafer having a process surface within a plasma reactor chamber for carrying out at least one plasma process; supplying at least one reactant gas flow at a selected flow rate to bypass the plasma reactor chamber for a period of time to achieve a pre-determined flow rate stability; and, redirecting the at least one reactant gas flow into the plasma reactor chamber to carry out the at least one plasma process.
摘要翻译：一种用于执行等离子体增强化学气相沉积（PECVD）工艺的方法和反应物气体旁通系统，其具有改进的气体流动稳定性以避免未结合的反应物前体和厚度不均匀性，该方法包括提供具有等离子体内的工艺表面的半导体工艺晶片反应室，用于进行至少一个等离子体工艺; 以选定的流速供应至少一个反应气体流以绕过等离子体反应器室一段时间以达到预定的流速稳定性; 以及将所述至少一个反应物气流重定向到所述等离子体反应器室中以执行所述至少一个等离子体过程。

5. 发明授权

US07176571B2 Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure 有权
标题翻译：氮化物阻挡层，以防止双重镶嵌结构中的金属（Cu）泄漏问题
公开(公告)号：US07176571B2
公开(公告)日：2007-02-13
申请号：US10753637
申请日：2004-01-08
申请人： Yi-Lung Cheng , Ying-Lung Wang
发明人： Yi-Lung Cheng , Ying-Lung Wang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76826
摘要： A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.
摘要翻译：公开了一种用于形成复合阻挡层的方法，该复合阻挡层也用作镶嵌工艺中的蚀刻停止。将SiC层沉积在CVD处理室中的衬底上，随后沉积氮化硅层以完成复合势垒层。 SiC层对衬底中的铜层表现出优异的粘附性，并且通过避免反应性Si + 4+物质并由此防止CuSi X X形成的方法形成。氮化硅层的厚度足以为金属离子提供优异的阻挡能力，但保持尽可能的薄，以使复合阻挡层的介电常数最小化。复合阻挡层在氧化灰化步骤期间提供优异的铜氧化性能，并且与使用常规氮化硅阻挡层相比，能够以较低的漏电流制造铜层。

6. 发明授权

US06979656B2 Carbon and halogen doped silicate glass dielectric layer and method for fabricating the same 失效
标题翻译：碳和卤素掺杂的硅酸盐玻璃介电层及其制造方法
公开(公告)号：US06979656B2
公开(公告)日：2005-12-27
申请号：US10729217
申请日：2003-12-04
申请人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
发明人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
IPC分类号： H01L21/31 , H01L21/316 , H01L21/76 , H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , C23C16/401 , H01L21/02126 , H01L21/02131 , H01L21/02211 , H01L21/02274 , H01L21/31629 , H01L21/31633 , H01L21/76802 , H01L21/76807 , H01L21/76835 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.
摘要翻译：制造电介质层的方法提供了当形成碳和卤素掺杂的硅酸盐玻璃介电层时与卤素源材料分开的碳源材料的使用。当形成碳和卤素掺杂的硅酸盐玻璃介电层时，使用单独的碳和卤素源材料提供了增强的工艺自由度。具有大于约3.0的介电常数的这种碳和卤素掺杂的硅酸盐玻璃介电层特别适用于镶嵌法中的本征平面化停止层。包含碳和卤素掺杂的硅酸盐玻璃的双层电介质层结构和不含卤素掺杂的碳掺杂的硅酸盐玻璃介电层在双镶嵌方法中是有用的。

7. 发明授权

US06759347B1 Method of forming in-situ SRO HDP-CVD barrier film 失效
标题翻译：形成原位SRO HDP-CVD阻挡膜的方法
公开(公告)号：US06759347B1
公开(公告)日：2004-07-06
申请号：US10401715
申请日：2003-03-27
申请人： Yi-Lung Cheng , Ming-Hwa Yoo , Sze-An Wu , Ying Lung Wang
发明人： Yi-Lung Cheng , Ming-Hwa Yoo , Sze-An Wu , Ying Lung Wang
IPC分类号： H01L2131
CPC分类号： C23C16/505 , C23C16/401 , H01L21/31629 , H01L21/76819 , H01L21/76829
摘要： A method of reducing plasma induced damage in semiconductor devices and fluorine damage to a metal containing layer including providing a semiconductor wafer including semiconductor devices including a gate oxide and a process surface including metal lines; carrying out a first high density plasma chemical vapor deposition (HDP-CVD) process to controllably produce a silicon rich oxide (SRO) layer including a relatively increased thickness at a center portion of the process surface compared to a peripheral portion of the process surface; and, carrying out a second HDP-CVD process in-situ to deposit a fluorine doped silicon dioxide layer over the SRO layer to fill a space between the metal lines.
摘要翻译：一种降低半导体器件中的等离子体诱发损伤的方法和对含金属层的氟损伤的方法，包括提供包括包括栅极氧化物的半导体器件和包括金属线的工艺表面的半导体晶片的半导体晶片; 执行第一高密度等离子体化学气相沉积（HDP-CVD）工艺，以可控地产生富硅氧化物（SRO）层，其与过程表面的周边部分相比在工艺表面的中心部分包括相对增加的厚度; 并且原位进行第二HDP-CVD工艺以在SRO层上沉积氟掺杂的二氧化硅层以填充金属线之间的空间。

8. 发明授权

US07420277B2 System for heat dissipation in semiconductor devices 有权
标题翻译：半导体器件散热系统
公开(公告)号：US07420277B2
公开(公告)日：2008-09-02
申请号：US10801475
申请日：2004-03-16
申请人： Hsien-Wei Chen , Jiun-Lin Yeh , Shin-Puu Jeng , Yi-Lung Cheng
发明人： Hsien-Wei Chen , Jiun-Lin Yeh , Shin-Puu Jeng , Yi-Lung Cheng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/528 , H01L21/76834 , H01L21/76837 , H01L23/4334 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.
摘要翻译：本公开提供了一种用于半导体器件中散热的方法和系统。在一个示例中，集成电路半导体器件包括半导体衬底; 连接到半导体衬底的一个或多个冶金层，并且所述一个或多个冶金层中的每一个包括：一个或多个导电线; 并且连接所述一个或多个导电线与所述一个或多个虚拟结构中的至少两个之间的一个或多个虚设结构; 以及一个或多个冶金层之间的一个或多个电介质层。

9. 发明申请

US20050124151A1 Novel method to deposit carbon doped SiO2 films with improved film quality 审中-公开
标题翻译：用于提高膜质量的新型沉积碳掺杂SiO 2膜的方法
公开(公告)号：US20050124151A1
公开(公告)日：2005-06-09
申请号：US10728215
申请日：2003-12-04
申请人： Yi-Lung Cheng , Ren-Haur Liu , Cheng-Hsiung Liu , Ying-Lang Wang , Hway-Chi Lin , Chien-Ming Chiu
发明人： Yi-Lung Cheng , Ren-Haur Liu , Cheng-Hsiung Liu , Ying-Lang Wang , Hway-Chi Lin , Chien-Ming Chiu
IPC分类号： C23C16/40 , H01L21/316 , H01L21/768 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/76819
摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.
摘要翻译：公开了一种用于在CVD室中沉积黑金刚石层的方法。三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。在所得到的金属互连中实现较低的漏电流和更高的击穿电压。

10. 发明申请

US20050112859A1 Method of forming a borderless contact opening featuring a composite tri-layer etch stop material 失效
标题翻译：形成具有复合三层蚀刻停止材料的无边界接触开口的方法
公开(公告)号：US20050112859A1
公开(公告)日：2005-05-26
申请号：US10718881
申请日：2003-11-21
申请人： Yi-Lung Cheng , Shih-Chia Cheng
发明人： Yi-Lung Cheng , Shih-Chia Cheng
IPC分类号： H01L21/31 , H01L21/311 , H01L21/44 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of forming an opening in a stack of insulator layers featuring an underlying etch stop layer comprised of a tri-layer insulator composite, has been developed. The tri-layer insulator composite comprised of a bottom silicon rich, silicon oxide layer and a top silicon nitride layer, is first formed on a conductive region of a semiconductor substrate. After deposition of overlying insulator layers a photoresist shape is used as a etch mask to allow the desired contact or via hole shape to be defined in the overlying insulator layers via a first phase of an anisotropic dry etch procedure, with the first phase of the dry etching procedure terminating at the top surface of the silicon nitride layer. An over etch procedure used to insure complete removal of overlying insulator layer from the surface of the tri-layer insulator composite, is next performed as a second phase of the anisotropic dry etch procedure. The high etch rate ratio of insulator layer to silicon nitride allows the over etch cycle to be successfully accomplished without risk to underlying materials. A third phase of the anisotropic dry etch procedure selectively removes the silicon nitride layer and subsequently selectively removes the silicon rich, silicon oxide layer without damage to the now exposed conductive region, resulting in definition of the desired contact or via hole openings in the stack of insulator layers.
摘要翻译：已经开发了在堆叠的绝缘体层中形成开口的方法，其特征在于由三层绝缘体复合材料构成的下面的蚀刻停止层。首先在半导体衬底的导电区域上形成由富硅底层，氧化硅层和顶部氮化硅层组成的三层绝缘体复合体。在沉积上覆绝缘体层之后，使用光致抗蚀剂形状作为蚀刻掩模，以允许通过各向异性干蚀刻程序的第一阶段在上覆绝缘体层中限定所需的接触或通孔形状，其中第一相干燥蚀刻过程终止于氮化硅层的顶表面。接下来，进行用于确保从三层绝缘体复合材料的表面完全去除上覆绝缘体层的过蚀刻程序作为各向异性干蚀刻工艺的第二阶段。绝缘体层与氮化硅的高蚀刻速率比允许成功地实现过蚀刻循环，而不会对下面的材料造成风险。各向异性干蚀刻过程的第三阶段选择性地去除氮化硅层，随后选择性地除去富含硅的氧化硅层，而不损害现在暴露的导电区域，导致定义了堆叠中的所需接触或通孔开口绝缘体层。

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