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1. 发明申请

US20120063090A1 COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：堆叠式包装的冷却机构及其制造方法
公开(公告)号：US20120063090A1
公开(公告)日：2012-03-15
申请号：US12878319
申请日：2010-09-09
申请人： Yi-Li HSIAO , Chen-Hua YU , Da-Yuan SHIH , Chih-Hang TUNG , Chun Hui YU
发明人： Yi-Li HSIAO , Chen-Hua YU , Da-Yuan SHIH , Chih-Hang TUNG , Chun Hui YU
IPC分类号： H01L23/34 , H01L21/50
CPC分类号： H01L23/44 , H01L23/473 , H01L24/14 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/165 , H01L25/18 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/01019 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1461 , H01L2924/157 , H01L2924/00
摘要： An apparatus for cooling a stacked die package comprises a substrate, a first die above the substrate, a second die above the first die, and a housing containing the first and second dies. The housing seals the first and second dies from the environment. The apparatus further includes a cooling fluid in fluid communication with the first die and the second die to transfer the heat from the dies to the housing.
摘要翻译：一种用于冷却堆叠管芯封装的装置，包括：衬底，在衬底上方的第一裸片，在第一裸片上方的第二裸片;以及容纳第一和第二裸片的外壳。壳体将第一和第二模具与环境密封。该装置还包括与第一模具和第二模具流体连通的冷却流体，以将来自模具的热量传递到壳体。

2. 发明申请

US20130307144A1 THREE-DIMENSIONAL CHIP STACK AND METHOD OF FORMING THE SAME 有权
标题翻译：三维芯片堆叠及其形成方法
公开(公告)号：US20130307144A1
公开(公告)日：2013-11-21
申请号：US13544746
申请日：2012-07-09
申请人： Chen-Hua YU , Da-Yuan SHIH , Chih-Hang TUNG
发明人： Chen-Hua YU , Da-Yuan SHIH , Chih-Hang TUNG
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/48 , H01L23/3185 , H01L23/3192 , H01L23/488 , H01L23/52 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/05611 , H01L2224/05618 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05676 , H01L2224/05681 , H01L2224/1134 , H01L2224/1146 , H01L2224/11466 , H01L2224/11823 , H01L2224/11825 , H01L2224/1184 , H01L2224/13005 , H01L2224/13019 , H01L2224/13147 , H01L2224/13562 , H01L2224/13582 , H01L2224/13611 , H01L2224/13618 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13669 , H01L2224/13673 , H01L2224/13676 , H01L2224/29011 , H01L2224/29035 , H01L2224/2919 , H01L2224/73103 , H01L2224/73203 , H01L2224/81193 , H01L2224/81205 , H01L2224/8183 , H01L2224/81895 , H01L2224/83191 , H01L2224/83193 , H01L2224/94 , H01L2924/00014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/014 , H01L2924/01029 , H01L2924/206 , H01L2224/81 , H01L2924/0665 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A three dimensional (3D) chip stack includes a first chip bonded to a second chip. The first chip includes a first bump structure overlying the first substrate, and the second chip includes a second bump structure overlying the second substrate. The first bump structure is attached to the second bump structure, and a joining region is formed between the first bump structure and the second bump structure. The joining region is a solderless region which includes a noble metal.
摘要翻译：三维（3D）芯片堆叠包括结合到第二芯片的第一芯片。第一芯片包括覆盖第一基板的第一凸块结构，并且第二芯片包括覆盖第二基板的第二凸块结构。第一凸块结构附接到第二凸块结构，并且在第一凸块结构和第二凸块结构之间形成接合区域。接合区域是包括贵金属的无焊区域。

3. 发明申请

US20130221074A1 SOLDER BUMP STRETCHING METHOD 审中-公开
标题翻译：焊膏压延方法
公开(公告)号：US20130221074A1
公开(公告)日：2013-08-29
申请号：US13406198
申请日：2012-02-27
申请人： Cheng-Chang WEI , Su-Chun YANG , Hsiao-Yun CHEN , Chih-Hang TUNG , Da-Yuan SHIH , Chen-Hua YU
发明人： Cheng-Chang WEI , Su-Chun YANG , Hsiao-Yun CHEN , Chih-Hang TUNG , Da-Yuan SHIH , Chen-Hua YU
IPC分类号： H05K13/04
CPC分类号： H05K13/0465 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/13014 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16057 , H01L2224/16058 , H01L2224/16225 , H01L2224/16227 , H01L2224/75252 , H01L2224/75744 , H01L2224/75745 , H01L2224/81121 , H01L2224/81191 , H01L2224/81815 , H01L2224/8193 , H01L2924/00013 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/13099 , H01L2224/05099 , H01L2224/05599
摘要： A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down.
摘要翻译：一种方法包括将焊料凸块加热到焊料凸块的熔化温度以上。焊料凸块被拉伸以增加焊料凸块的高度。焊锡凸块被冷却。

4. 发明申请

US20130147032A1 PASSIVATION LAYER FOR PACKAGED CHIP 有权
标题翻译：包装芯片的钝化层
公开(公告)号：US20130147032A1
公开(公告)日：2013-06-13
申请号：US13313747
申请日：2011-12-07
申请人： Shin-Puu JENG , Wei-Cheng WU , Shang-Yun HOU , Chen-Hua YU , Tzuan-Horng LIU , Tzu-Wei CHIU , Kuo-Ching HSU
发明人： Shin-Puu JENG , Wei-Cheng WU , Shang-Yun HOU , Chen-Hua YU , Tzuan-Horng LIU , Tzu-Wei CHIU , Kuo-Ching HSU
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L22/34 , G01R31/2884 , H01L21/76885 , H01L22/32 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/02126 , H01L2224/0401 , H01L2224/05001 , H01L2224/0554 , H01L2224/10126 , H01L2224/13005 , H01L2224/16225 , H01L2924/12044 , H01L2924/15311 , H01L2924/00
摘要： The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.
摘要翻译：上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。这种界面电阻的降低导致金属凸块的电阻降低。

5. 发明申请

US20110285005A1 PACKAGE SYSTEMS HAVING INTERPOSERS 有权
标题翻译：包装系统
公开(公告)号：US20110285005A1
公开(公告)日：2011-11-24
申请号：US12781960
申请日：2010-05-18
申请人： Yung-Chi LIN , Jing-Cheng LIN , Chen-Hua YU
发明人： Yung-Chi LIN , Jing-Cheng LIN , Chen-Hua YU
IPC分类号： H01L23/538
CPC分类号： H01L21/4857 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/768 , H01L23/295 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/03 , H01L24/11 , H01L24/19 , H01L24/24 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2224/02331 , H01L2224/02372 , H01L2224/0239 , H01L2224/0401 , H01L2224/12105 , H01L2224/16225 , H01L2224/24227 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.
摘要翻译：封装系统包括设置在插入器上的第一集成电路。所述插入器包括至少一个包含穿过所述至少一个模塑复合层的多个电连接结构的模塑复合层。第一互连结构设置在至少一个模塑复合层的第一表面上并与多个电连接结构电耦合。第一集成电路与第一互连结构电耦合。

6. 发明申请

US20110027944A1 METHOD OF FORMING ELECTRICAL CONNECTIONS 有权
标题翻译：形成电气连接的方法
公开(公告)号：US20110027944A1
公开(公告)日：2011-02-03
申请号：US12768025
申请日：2010-04-27
申请人： Chung-Shi LIU , Shin-Puu JENG , Mirng-Ji LII , Chen-Hua YU
发明人： Chung-Shi LIU , Shin-Puu JENG , Mirng-Ji LII , Chen-Hua YU
IPC分类号： H01L21/768 , H01L21/56
CPC分类号： H01L23/3171 , H01L21/563 , H01L23/525 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/10126 , H01L2224/1147 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/73203 , H01L2924/00013 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2224/13099
摘要： A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material.
摘要翻译：形成与半导体晶片的电连接的方法。提供了包括绝缘层的半导体晶片。绝缘层具有表面。在绝缘层的表面上形成图案化掩模层。图案化掩模层通过多个孔暴露绝缘层的表面的部分。多个孔的部分填充有包含铜的金属材料以形成细长的金属材料柱。金属材料的细长柱具有侧壁表面。去除图案化的掩模层以暴露金属材料的细长柱的侧壁表面。保护层形成在金属材料的细长柱的暴露的侧壁表面上。

7. 发明申请

US20110001250A1 METHOD AND STRUCTURE FOR ADHESION OF INTERMETALLIC COMPOUND (IMC) ON CU PILLAR BUMP 有权
标题翻译：金属间化合物（IMC）粘附在铜管柱上的方法和结构
公开(公告)号：US20110001250A1
公开(公告)日：2011-01-06
申请号：US12825822
申请日：2010-06-29
申请人： Jing-Cheng LIN , Chen-Hua YU
发明人： Jing-Cheng LIN , Chen-Hua YU
IPC分类号： H01L23/488 , B05D5/12 , B32B3/00
CPC分类号： H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/11462 , H01L2224/1147 , H01L2224/11901 , H01L2224/1308 , H01L2224/13084 , H01L2224/13147 , H01L2224/13583 , H01L2224/13611 , H01L2224/13655 , H01L2224/16 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , Y10T428/24612 , H01L2924/00014 , H01L2924/01083 , H01L2924/01015 , H01L2224/13099 , H01L2924/00 , H01L2224/1146
摘要： A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer.
摘要翻译：提供了一种用于金属间化合物（IMC）对Cu柱凸块的良好粘附的方法和结构。该方法包括沉积Cu以形成Cu柱层，在Cu柱层的顶部上沉积扩散阻挡层，并在扩散阻挡层的顶部上沉积Cu覆盖层，其中形成金属间化合物（IMC）扩散阻挡层，Cu覆盖层和位于Cu覆盖层顶部的焊料层。 IMC对Cu柱结构具有良好的粘附性，IMC的厚度可由Cu覆盖层的厚度控制，扩散阻挡层限制Cu从Cu柱层到焊料层的扩散。该方法可以进一步包括在沉积Cu覆盖层之前在扩散阻挡层的顶部沉积薄层以获得润湿性。

8. 发明申请

US20100330788A1 THIN WAFER HANDLING STRUCTURE AND METHOD 有权
标题翻译：薄波处理结构与方法
公开(公告)号：US20100330788A1
公开(公告)日：2010-12-30
申请号：US12818362
申请日：2010-06-18
申请人： Chen-Hua YU , Kuo-Ching HSU , Chen-Shien CHEN , Ching-Wen HSIAO
发明人： Chen-Hua YU , Kuo-Ching HSU , Chen-Shien CHEN , Ching-Wen HSIAO
IPC分类号： H01L21/265 , H01L21/26 , H01L21/306 , H01L21/3205 , B32B7/12 , C23C14/34 , B24B1/00
CPC分类号： H01L21/187 , H01L21/6835 , H01L2221/68318 , H01L2221/68327 , H01L2221/68381 , Y10T428/1476
摘要： A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.
摘要翻译：薄晶片处理结构包括半导体晶片，可通过施加能量释放的释放层，可通过溶剂除去的粘合剂层和载体，其中通过涂覆或层压将剥离层施加在载体上，通过涂布或层压将粘合剂层施加在半导体晶片上，半导体晶片和载体与剥离层和粘合剂层粘合在一起。该方法包括在载体上施加剥离层，在半导体晶片上施加粘合剂层，粘合载体和半导体晶片，通过在释放层上施加能量来释放载体，例如， UV或激光，并且通过溶剂清洁半导体的表面以除去粘合剂层的任何残余物。

9. 发明申请

US20100072632A1 BOND PAD STRUCTURE HAVING DUMMY PLUGS AND/OR PATTERNS FORMED THEREAROUND 有权
标题翻译：具有形式的DUMMY PLUGS和/或图案的BOND PAD结构
公开(公告)号：US20100072632A1
公开(公告)日：2010-03-25
申请号：US12233974
申请日：2008-09-19
申请人： Chen-Hua YU , Tien-I BAO
发明人： Chen-Hua YU , Tien-I BAO
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L24/05 , H01L23/5226 , H01L24/06 , H01L24/45 , H01L2224/04042 , H01L2224/05093 , H01L2224/05097 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48666 , H01L2224/48684 , H01L2224/48724 , H01L2224/48747 , H01L2224/48755 , H01L2224/48766 , H01L2224/48784 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48866 , H01L2224/48881 , H01L2224/48884 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19043 , H01L2924/351 , H01L2924/00014 , H01L2224/45147 , H01L2924/00 , H01L2224/48824 , H01L2224/48744 , H01L2224/48781 , H01L2224/48681
摘要： A semiconductor structure is provided. In one embodiment, a bond pad is formed above one or more underlying layers of a substrate. A plurality of dummy plugs are spaced around the bond pad, the plurality of dummy plugs substantially vertically traversing the one or more underlying layers, wherein the plurality of dummy plugs anchor at least two of the underlying layers together to achieve improved mechanical strength.
摘要翻译：提供半导体结构。在一个实施例中，在衬底的一个或多个下层上方形成接合焊盘。多个虚拟插头围绕接合焊盘间隔开，多个虚拟插头基本垂直地穿过一个或多个下层，其中多个虚拟插头将至少两个下面的层固定在一起以实现改进的机械强度。

10. 发明申请

US20100084718A1 ADVANCED METAL GATE METHOD AND DEVICE 有权
标题翻译：高级金属门的方法和装置
公开(公告)号：US20100084718A1
公开(公告)日：2010-04-08
申请号：US12354558
申请日：2009-01-15
申请人： Chung-Shi LIU , Hsiang-Yi WANG , Cheng-Tung LIN , Chen-Hua YU
发明人： Chung-Shi LIU , Hsiang-Yi WANG , Cheng-Tung LIN , Chen-Hua YU
IPC分类号： H01L29/78 , H01L21/283 , H01L21/336
CPC分类号： H01L21/28088 , H01L21/265 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/51 , H01L29/78
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.
摘要翻译：本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到第一栅极结构中的第一金属层和高k电介质。

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