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1. 发明申请

US20050258499A1 Resistance-reduced semiconductor device and methods for fabricating the same 有权
标题翻译：电阻降低半导体器件及其制造方法
公开(公告)号：US20050258499A1
公开(公告)日：2005-11-24
申请号：US11190913
申请日：2005-07-28
申请人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
发明人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L29/06 , H01L29/76 , H01L31/062
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/76897 , H01L29/665 , H01L29/6659
摘要： Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.
摘要翻译：半导体器件及其制造方法。半导体器件包括具有覆盖源极/漏极区域的金属化双层的电阻降低的晶体管及其栅电极。具有导电接触的第一介电层覆盖电阻减小的晶体管。具有第一导电特征的第二介电层覆盖在第一介电层上。具有第二导电特征的第三电介质层覆盖在第二电介质层上，在源极/漏极区域或栅极电极层之一上形成向下至金属化双层的顶表面的导电通路。

2. 发明授权

US07256498B2 Resistance-reduced semiconductor device and methods for fabricating the same 有权
标题翻译：电阻降低半导体器件及其制造方法
公开(公告)号：US07256498B2
公开(公告)日：2007-08-14
申请号：US11190913
申请日：2005-07-28
申请人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
发明人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
IPC分类号： H01L27/04
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/76897 , H01L29/665 , H01L29/6659
摘要： Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.
摘要翻译：半导体器件及其制造方法。半导体器件包括具有覆盖源极/漏极区域的金属化双层的电阻降低的晶体管及其栅电极。具有导电接触的第一介电层覆盖电阻减小的晶体管。具有第一导电特征的第二介电层覆盖在第一介电层上。具有第二导电特征的第三电介质层覆盖在第二电介质层上，在源极/漏极区域或栅极电极层之一上形成向下至金属化双层的顶表面的导电通路。

3. 发明申请

US20050285268A1 Alternative interconnect structure for semiconductor devices 有权
标题翻译：半导体器件的替代互连结构
公开(公告)号：US20050285268A1
公开(公告)日：2005-12-29
申请号：US10877103
申请日：2004-06-25
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Chun Huang
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Chun Huang
IPC分类号： H01L21/311 , H01L21/336 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76802 , H01L21/31133 , H01L21/31138 , H01L21/76895
摘要： A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.
摘要翻译：半导体互连结构包括设置在接触表面上的有机和/或感光蚀刻缓冲层。该结构还提供了形成在蚀刻缓冲层上的层间电介质。用于形成互连结构的方法包括蚀刻以在层间电介质中形成开口，蚀刻操作在蚀刻缓冲层上或其上终止。去除蚀刻缓冲层以暴露接触表面，使用可以包括湿法蚀刻，灰化或DUV曝光，随后显影的其它技术或不会导致对接触表面损坏的去除工艺。接触表面可以是导电材料，例如硅化物，硅化物或金属合金。

4. 发明申请

US20050212058A1 Resistance-reduced semiconductor device and fabrication thereof 审中-公开
标题翻译：电阻降低的半导体器件及其制造
公开(公告)号：US20050212058A1
公开(公告)日：2005-09-29
申请号：US10806217
申请日：2004-03-23
申请人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
发明人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L29/06 , H01L29/76 , H01L31/062
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6659
摘要： A resistance-reduced semiconductor device and fabrication thereof. The semiconductor device of the invention includes a semiconductor device body exposing at least one silicon-containing portion, a metal silicide layer with a first resistivity overlying the silicon-containing portion and a conductor layer with a second resistivity overlying the metal silicide layer, wherein the second resistivity is smaller than the first resistivity.
摘要翻译：一种电阻降低半导体器件及其制造。本发明的半导体器件包括暴露至少一个含硅部分的半导体器件本体，覆盖硅含量部分的第一电阻率的金属硅化物层和覆盖金属硅化物层的第二电阻率的导体层，其中第二电阻率小于第一电阻率。

5. 发明授权

US07341935B2 Alternative interconnect structure for semiconductor devices 有权
标题翻译：半导体器件的替代互连结构
公开(公告)号：US07341935B2
公开(公告)日：2008-03-11
申请号：US10877103
申请日：2004-06-25
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Chun Huang
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Chun Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31133 , H01L21/31138 , H01L21/76895
摘要： A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.
摘要翻译：半导体互连结构包括设置在接触表面上的有机和/或感光蚀刻缓冲层。该结构还提供了形成在蚀刻缓冲层上的层间电介质。用于形成互连结构的方法包括蚀刻以在层间电介质中形成开口，蚀刻操作在蚀刻缓冲层上或其上终止。去除蚀刻缓冲层以暴露接触表面，使用可以包括湿法蚀刻，灰化或DUV曝光，随后显影的其它技术或不会导致对接触表面损坏的去除工艺。接触表面可以是导电材料，例如硅化物，硅化物或金属合金。

6. 发明申请

US20060154478A1 Contact hole structures and contact structures and fabrication methods thereof 有权
标题翻译：接触孔结构及接触结构及其制造方法
公开(公告)号：US20060154478A1
公开(公告)日：2006-07-13
申请号：US11035325
申请日：2005-01-12
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76835
摘要： Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.
摘要翻译：公开了形成接触孔结构的方法和结构。这些方法首先在衬底上形成基本上无硅的材料层。在基本无硅材料层上形成材料层。在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。此外，在接触孔中形成导电层以形成接触结构。

7. 发明申请

US20060063322A1 Transistor with high dielectric constant gate and method for forming the same 有权
标题翻译：具有高介电常数栅极的晶体管及其形成方法
公开(公告)号：US20060063322A1
公开(公告)日：2006-03-23
申请号：US10946494
申请日：2004-09-21
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Ju-Chien Chiang
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Ju-Chien Chiang
IPC分类号： H01L21/8238 , H01L21/302
CPC分类号： H01L29/66553 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4975 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.
摘要翻译：半导体器件提供了一种栅极结构，其包括在导电材料的下面和沿着导电材料的侧面形成的导电部分和高k电介质材料。除了高k电介质材料之外，可以使用诸如栅极氧化物的附加栅极介电材料。形成结构的方法包括在有机材料中形成开口，在开口内和有机材料上形成高k电介质材料和导电材料，然后使用化学机械抛光去除高k电介质材料和导电材料从门区域外的区域。

8. 发明申请

US20070235823A1 CMOS devices with improved gap-filling 有权
标题翻译：具有改进间隙填充的CMOS器件
公开(公告)号：US20070235823A1
公开(公告)日：2007-10-11
申请号：US11393369
申请日：2006-03-30
申请人： Ju-Wang Hsu , Chih-Hsin Ko , Jyu-Horng Shieh , Baw-Ching Perng , Syun-Ming Jang
发明人： Ju-Wang Hsu , Chih-Hsin Ko , Jyu-Horng Shieh , Baw-Ching Perng , Syun-Ming Jang
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843 , Y10S438/981
摘要： A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.
摘要翻译：半导体结构包括衬底和在衬底的第一区域上的第一MOS器件，其中第一MOS器件包括第一间隔衬垫。半导体结构还包括在第二区域上的第二MOS器件，其中第二MOS器件包括第二间隔衬垫。在第一MOS器件上形成具有第一厚度的第一应力膜，并直接在第一间隔衬垫上。在第二MOS器件上形成具有第二厚度的第二应力膜，并且直接在第二间隔衬垫上。第一和第二应力膜可以由相同的材料形成。

9. 发明授权

US07271448B2 Multiple gate field effect transistor structure 有权
标题翻译：多栅场效应晶体管结构
公开(公告)号：US07271448B2
公开(公告)日：2007-09-18
申请号：US11057423
申请日：2005-02-14
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Tang Xuan , Sheng-Da Liu
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Tang Xuan , Sheng-Da Liu
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).
摘要翻译：一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

10. 发明授权

US07875547B2 Contact hole structures and contact structures and fabrication methods thereof 有权
标题翻译：接触孔结构及接触结构及其制造方法
公开(公告)号：US07875547B2
公开(公告)日：2011-01-25
申请号：US11035325
申请日：2005-01-12
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76835
摘要： Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.
摘要翻译：公开了形成接触孔结构的方法和结构。这些方法首先在衬底上形成基本上无硅的材料层。在基本无硅材料层上形成材料层。在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。此外，在接触孔中形成导电层以形成接触结构。

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