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1. 发明授权

US07271448B2 Multiple gate field effect transistor structure 有权
标题翻译：多栅场效应晶体管结构
公开(公告)号：US07271448B2
公开(公告)日：2007-09-18
申请号：US11057423
申请日：2005-02-14
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Tang Xuan , Sheng-Da Liu
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Tang Xuan , Sheng-Da Liu
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).
摘要翻译：一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

2. 发明申请

US20060180854A1 Multiple gate field effect transistor structure 有权
标题翻译：多栅场效应晶体管结构
公开(公告)号：US20060180854A1
公开(公告)日：2006-08-17
申请号：US11057423
申请日：2005-02-14
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Xuan , Sheng-Da Liu
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Xuan , Sheng-Da Liu
IPC分类号： H01L31/113
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).
摘要翻译：一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

3. 发明授权

US07425740B2 Method and structure for a 1T-RAM bit cell and macro 有权
标题翻译： 1T-RAM位元和宏的方法和结构
公开(公告)号：US07425740B2
公开(公告)日：2008-09-16
申请号：US11246318
申请日：2005-10-07
申请人： Sheng-Da Liu , Hung-Wei Chen , Chang-Yun Chang , Zhong Tang Xuan , Ju-Wang Hsu
发明人： Sheng-Da Liu , Hung-Wei Chen , Chang-Yun Chang , Zhong Tang Xuan , Ju-Wang Hsu
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L27/01 , H01L27/12
CPC分类号： H01L28/82 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10879 , H01L27/10894 , H01L27/10897 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET transistor and MIM capacitor are formed in a memory region and an asymmetric processing method is disclosed, which allows planar MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM cell and additional transistors may be combined to form a macro cell, multiple macro cells may form an integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.
摘要翻译：提供一个晶体管（1T-RAM）位单元及其制造方法。提供了一种金属 - 绝缘体金属（MIM）电容器结构及其制造方法，其集成工艺包括用于1T-RAM位元的finFET晶体管。在一些实施例中，finFET晶体管和MIM电容器形成在存储区域中，并且公开了一种不对称处理方法，其允许在单个器件的另一个区域中形成平面MOSFET晶体管。在一些实施例中，可以组合1T-RAM单元和附加晶体管以形成宏小区，多个宏小区可以形成集成电路。 MIM电容器可以包括纳米颗粒或纳米结构以增加有效电容。 finFET晶体管可以形成在绝缘体上。 MIM电容器可以形成在衬底上方的层间绝缘体层中。提供用于制造结构的方法可以有利地使用常规的光掩模。

4. 发明申请

US20070080387A1 Method and structure for a 1T-RAM bit cell and macro 有权
标题翻译： 1T-RAM位元和宏的方法和结构
公开(公告)号：US20070080387A1
公开(公告)日：2007-04-12
申请号：US11246318
申请日：2005-10-07
申请人： Sheng-Da Liu , Hung-Wei Chen , Chang-Yun Chang , Zhong Xuan , Ju-Wang Hsu
发明人： Sheng-Da Liu , Hung-Wei Chen , Chang-Yun Chang , Zhong Xuan , Ju-Wang Hsu
IPC分类号： H01L27/108
CPC分类号： H01L28/82 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10879 , H01L27/10894 , H01L27/10897 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET transistor and MIM capacitor are formed in a memory region and an asymmetric processing method is disclosed, which allows planar MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM cell and additional transistors may be combined to form a macro cell, multiple macro cells may form an integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.
摘要翻译：提供一个晶体管（1T-RAM）位单元及其制造方法。提供了一种金属 - 绝缘体金属（MIM）电容器结构及其制造方法，其集成工艺包括用于1T-RAM位元的finFET晶体管。在一些实施例中，finFET晶体管和MIM电容器形成在存储区域中，并且公开了一种不对称处理方法，其允许在单个器件的另一个区域中形成平面MOSFET晶体管。在一些实施例中，可以组合1T-RAM单元和附加晶体管以形成宏小区，多个宏小区可以形成集成电路。 MIM电容器可以包括纳米颗粒或纳米结构以增加有效电容。 finFET晶体管可以形成在绝缘体上。 MIM电容器可以形成在衬底上方的层间绝缘体层中。提供用于制造结构的方法可以有利地使用常规的光掩模。

5. 再颁专利

USRE45180E1 Structure for a multiple-gate FET device and a method for its fabrication 有权
标题翻译：多栅极FET器件的结构及其制造方法
公开(公告)号：USRE45180E1
公开(公告)日：2014-10-07
申请号：US12792373
申请日：2010-06-02
申请人： Hung-Wei Chen , Tang-Xuan Zhong , Sheng-Da Liu , Chang-Yun Chang , Ping-Kun Wu , Chao-Hsiung Wang , Fu-Liang Yang
发明人： Hung-Wei Chen , Tang-Xuan Zhong , Sheng-Da Liu , Chang-Yun Chang , Ping-Kun Wu , Chao-Hsiung Wang , Fu-Liang Yang
IPC分类号： H01L21/311 , H01L21/00 , H01L21/84 , H01L21/8238 , H01L21/336 , H01L27/085 , H01L29/06 , H01L29/04
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L21/823456 , H01L29/66795 , H01L29/7851
摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
摘要翻译：提供了一种用于形成半导体器件的方法和使用该方法制造的器件。在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。沟槽部分地填充有电介质材料。去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

6. 发明授权

US07381649B2 Structure for a multiple-gate FET device and a method for its fabrication 有权
标题翻译：多栅极FET器件的结构及其制造方法
公开(公告)号：US07381649B2
公开(公告)日：2008-06-03
申请号：US11192494
申请日：2005-07-29
申请人： Hung-Wei Chen , Tang-Xuan Zhong , Sheng-Da Liu , Chang-Yun Chang , Ping-Kun Wu , Chao-Hsiung Wang , Fu-Liang Yang
发明人： Hung-Wei Chen , Tang-Xuan Zhong , Sheng-Da Liu , Chang-Yun Chang , Ping-Kun Wu , Chao-Hsiung Wang , Fu-Liang Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L21/823456 , H01L29/66795 , H01L29/7851
摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
摘要翻译：提供了一种用于形成半导体器件的方法和使用该方法制造的器件。在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。沟槽部分地填充有电介质材料。去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

7. 发明申请

US20080296702A1 Integrated circuit structures with multiple FinFETs 有权
标题翻译：具有多个FinFET的集成电路结构
公开(公告)号：US20080296702A1
公开(公告)日：2008-12-04
申请号：US11807652
申请日：2007-05-30
申请人： Tsung-Lin Lee , Chang-Yun Chang , Sheng-Da Liu , Fu-Liang Yang
发明人： Tsung-Lin Lee , Chang-Yun Chang , Sheng-Da Liu , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823437 , H01L21/823431 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/165 , H01L29/41791 , H01L29/66795 , H01L29/7843 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.
摘要翻译：半导体结构包括半导体衬底; 以及在半导体衬底的表面处的第一Fin场效应晶体管（FinFET）和第二FinFET。第一个FinFET包括第一个鳍; 以及在第一鳍的顶表面和侧壁上的第一栅电极。第二FinFET包括通过鳍片空间与第一鳍片间隔开的第二鳍片; 以及在第二鳍的顶表面和侧壁上的第二栅电极。第二栅电极与第一栅电极电断开。第一和第二栅电极具有大于翅片空间的约一半的栅极高度。

8. 发明授权

US08174073B2 Integrated circuit structures with multiple FinFETs 有权
标题翻译：具有多个FinFET的集成电路结构
公开(公告)号：US08174073B2
公开(公告)日：2012-05-08
申请号：US11807652
申请日：2007-05-30
申请人： Tsung-Lin Lee , Chang-Yun Chang , Sheng-Da Liu , Fu-Liang Yang
发明人： Tsung-Lin Lee , Chang-Yun Chang , Sheng-Da Liu , Fu-Liang Yang
IPC分类号： H01L27/12
CPC分类号： H01L21/823437 , H01L21/823431 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/165 , H01L29/41791 , H01L29/66795 , H01L29/7843 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.
摘要翻译：半导体结构包括半导体衬底; 以及在半导体衬底的表面处的第一Fin场效应晶体管（FinFET）和第二FinFET。第一个FinFET包括第一个鳍; 以及在第一鳍的顶表面和侧壁上的第一栅电极。第二FinFET包括通过鳍片空间与第一鳍片间隔开的第二鳍片; 以及在第二鳍的顶表面和侧壁上的第二栅电极。第二栅电极与第一栅电极电断开。第一和第二栅电极具有大于翅片空间的约一半的栅极高度。

9. 发明授权

US09953885B2 STI shape near fin bottom of Si fin in bulk FinFET 有权
公开(公告)号：US09953885B2
公开(公告)日：2018-04-24
申请号：US12843693
申请日：2010-07-26
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L21/76 , H01L21/84 , H01L21/762 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/845 , H01L21/76224 , H01L21/823431 , H01L29/66795
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

10. 发明授权

US09484462B2 Fin structure of fin field effect transistor 有权
标题翻译：翅片场效应晶体管的鳍结构
公开(公告)号：US09484462B2
公开(公告)日：2016-11-01
申请号：US12766233
申请日：2010-04-23
申请人： Feng Yuan , Hung-Ming Chen , Tsung-Lin Lee , Chang-Yun Chang , Clement Hsingjen Wann
发明人： Feng Yuan , Hung-Ming Chen , Tsung-Lin Lee , Chang-Yun Chang , Clement Hsingjen Wann
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/66795 , H01L21/308 , H01L29/7851 , H01L29/7853
摘要： An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.
摘要翻译：鳍状场效应晶体管的示例性结构包括：包括主表面的衬底; 多个翅片结构，从所述基底的主表面突出，其中每个翅片结构包括在翅片结构的侧壁与主表面成85度角的过渡位置处分离的上部和下部，其中所述上部具有基本上垂直于所述基底的主表面的侧壁和具有第一宽度的顶表面，其中所述下部具有在所述上部的相对侧上的锥形侧壁和具有第二宽度的基部宽度大于第一宽度; 以及在翅片结构之间的多个隔离结构，其中每个隔离结构从基板的主表面延伸到过渡位置上方的点。

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