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1. 发明授权

US08765553B2 Nonvolatile memory array having modified channel region interface 有权
标题翻译：具有修改的通道区域接口的非易失性存储器阵列
公开(公告)号：US08765553B2
公开(公告)日：2014-07-01
申请号：US12782553
申请日：2010-05-18
申请人： Yi Ying Liao
发明人： Yi Ying Liao
IPC分类号： H01L21/336
CPC分类号： G11C16/0475 , G11C16/10
摘要： Nonvolatile memory has a modified channel region interface, such as a raised source and drain or a recessed channel region.
摘要翻译：非易失性存储器具有修改的通道区域接口，例如升高的源极和漏极或凹陷沟道区域。

2. 发明授权

US07646637B2 Nonvolatile memory having modified channel region interface 有权
标题翻译：非易失性存储器具有修改的通道区域接口
公开(公告)号：US07646637B2
公开(公告)日：2010-01-12
申请号：US11775077
申请日：2007-07-09
申请人： Yi Ying Liao
发明人： Yi Ying Liao
IPC分类号： G11C16/04
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/42352 , H01L29/513
摘要： A nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region is included.
摘要翻译：包括具有修改的通道区域界面的非易失性存储器，例如升高的源极和漏极或凹陷沟道区域。

3. 发明授权

US07133317B2 Method and apparatus for programming nonvolatile memory 有权
标题翻译：用于非易失性存储器编程的方法和装置
公开(公告)号：US07133317B2
公开(公告)日：2006-11-07
申请号：US11064316
申请日：2005-02-23
申请人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai
发明人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0475 , G11C16/0491
摘要： Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the program disturb effect, voltages are applied to neighboring nonvolatile memory cells, which takes advantage of the program disturb effect to program multiple cells quickly.
摘要翻译：编程非易失性存储单元受程序干扰影响，导致非易失性存储器的数据精度问题。不是屏蔽导致程序干扰效应的电压条件，而是将电压施加到相邻的非易失性存储单元，利用程序干扰效应来快速编程多个单元。

4. 发明授权

US07723757B2 Vertical nonvolatile memory cell, array, and operation 有权
标题翻译：垂直非易失性存储单元，阵列和操作
公开(公告)号：US07723757B2
公开(公告)日：2010-05-25
申请号：US11774452
申请日：2007-07-06
申请人： Tien Fan Ou , Wen-Jer Tsai , Hsuan Ling Kao , Yi Ying Liao
发明人： Tien Fan Ou , Wen-Jer Tsai , Hsuan Ling Kao , Yi Ying Liao
IPC分类号： H01L29/74
CPC分类号： G11C16/0416 , G11C16/10 , H01L27/1026 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/7923 , H01L29/7926
摘要： A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的垂直非易失性存储单元包括具有三个节点的电荷控制结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

5. 发明授权

US07397701B2 Method and apparatus for operating a string of charge trapping memory cells 有权
标题翻译：用于操作电荷俘获存储器单元串的方法和装置
公开(公告)号：US07397701B2
公开(公告)日：2008-07-08
申请号：US11279720
申请日：2006-04-13
申请人： Chih Chieh Yeh , Wen Jer Tsai , Yi Ying Liao
发明人： Chih Chieh Yeh , Wen Jer Tsai , Yi Ying Liao
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/3445 , G11C16/3459
摘要： An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.
摘要翻译：电荷捕获非易失性存储单元的阵列被布置在几列单元格中，每列单元排列成一串，例如NAND串。每个单元格不存储单个电荷存储状态。

6. 发明申请

US20080031046A1 Nonvolatile Memory Array Having Modified Channel Region Interface 有权
标题翻译：具有修改通道区域接口的非易失性存储器阵列
公开(公告)号：US20080031046A1
公开(公告)日：2008-02-07
申请号：US11775107
申请日：2007-07-09
申请人： Yi Ying Liao
发明人： Yi Ying Liao
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10
摘要： The technology relates to nonvolatile memory with a modified channel region such as a raised source and drain or a recessed channel region.
摘要翻译：该技术涉及具有改进的沟道区域的非易失性存储器，例如升高的源极和漏极或凹陷沟道区域。

7. 发明授权

US07746694B2 Nonvolatile memory array having modified channel region interface 有权
标题翻译：具有修改的通道区域接口的非易失性存储器阵列
公开(公告)号：US07746694B2
公开(公告)日：2010-06-29
申请号：US11775107
申请日：2007-07-09
申请人： Yi Ying Liao
发明人： Yi Ying Liao
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10
摘要： The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.
摘要翻译：该技术涉及具有改进的通道区域界面的非易失性存储器，例如升高的源极和漏极或凹陷沟道区域。

8. 发明申请

US20090080254A1 Gated Diode Nonvolatile Memory Cell Array 有权
标题翻译：门极二极管非易失性存储单元阵列
公开(公告)号：US20090080254A1
公开(公告)日：2009-03-26
申请号：US12326706
申请日：2008-12-02
申请人： Yi Ying Liao , Wen Jer Tsai , Chih Chieh Yeh
发明人： Yi Ying Liao , Wen Jer Tsai , Chih Chieh Yeh
IPC分类号： G11C16/02 , G11C11/36
CPC分类号： G11C11/36 , B82Y10/00 , G11C16/02 , G11C2216/06 , H01L27/1021 , H01L29/8616
摘要： A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.
摘要翻译：存储器集成电路具有垂直分层的存储器阵列。这些存储器阵列包括字线和位线。字线和位线之间的交点包括二极管和存储器状态存储元件。二极管和存储器存储元件连接在字线和位线之间。交叉处的二极管包括第一二极管节点和第二二极管节点。存储器集成电路的各个方面以各种方式电互连，例如相应的字线，对应的第一二极管节点或不同存储器阵列的相应的第二二极管节点电互连。存储器集成电路的各个方面以各种方式隔离，例如隔离不同存储器阵列的字线，第一二极管节点或第二二极管节点。

9. 发明申请

US20080067578A1 Nonvolatile Memory Having Modified Channel Region Interface 有权
标题翻译：具有修改频道区域接口的非易失性存储器
公开(公告)号：US20080067578A1
公开(公告)日：2008-03-20
申请号：US11775077
申请日：2007-07-09
申请人： Yi Ying Liao
发明人： Yi Ying Liao
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/42352 , H01L29/513
摘要： The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.
摘要翻译：该技术涉及具有改进的通道区域界面的非易失性存储器，例如升高的源极和漏极或凹陷沟道区域。

10. 发明授权

US07272043B2 Operation methods for a non-volatile memory cell in an array 有权
标题翻译：阵列中非易失性存储单元的操作方法
公开(公告)号：US07272043B2
公开(公告)日：2007-09-18
申请号：US11020269
申请日：2004-12-27
申请人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai
发明人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0483
摘要： A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.
摘要翻译：一种通过在选定字线的不同侧面施加不同的Vpass电压来减少电荷俘获层存储单元中的门扰动的方法。较高的Vpass电压用于传递较高的源极/漏极电压，较低的Vpass电压用于通过较低的源极/漏极电压。通过控制所选字线的不同侧的Vpass电压，可以减小施加Vpass电压时在栅极区域中建立的垂直场。减小的垂直场导致抑制的门扰动。该方法还包括新颖的位线偏置方案，其可以进一步减小垂直场，从而可进一步抑制门扰动，特别是在存储器单元阵列中。

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