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1. 发明授权

US08392660B2 Cache system including a plurality of processing units 有权
公开(公告)号：US08392660B2
公开(公告)日：2013-03-05
申请号：US12453782
申请日：2009-05-21
申请人： Yi Ge , Shinichiro Tago
发明人： Yi Ge , Shinichiro Tago
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/0811 , G06F12/128 , G06F2212/271
摘要： A cache system includes processing units operative to access a main memory device, caches coupled in one-to-one correspondence to the processing units, and a controller coupled to the caches to control data transfer between the caches and data transfer between the main memory and the caches, wherein the controller includes a memory configured to store first information and second information separately for each index, the first information indicating an order of oldness of entries in each one of the caches, and the second information indicating an order of oldness of entries for the plurality of the caches, and a logic circuit configured to select an entry to be evicted and its destination in response to the first and second information when an entry of an index corresponding to an accessed address is to be evicted from a cache corresponding to the processing unit that accesses the main memory device.

2. 发明申请

US20110093429A1 SEARCH DEVICE AND SEARCH METHOD 有权
标题翻译：搜索设备和搜索方法
公开(公告)号：US20110093429A1
公开(公告)日：2011-04-21
申请号：US12974877
申请日：2010-12-21
申请人： Yi Ge , Shinichiro Tago
发明人： Yi Ge , Shinichiro Tago
IPC分类号： G06N5/02
CPC分类号： G06F17/30911
摘要： A search device includes an accelerator and a CPU. The accelerator includes a plurality of search cores and a scheduler. The scheduler is configured to distribute target text to the search cores in units of records ordered by record sequence number, and the search cores are configured to perform automaton matching on the distributed records in a parallel fashion. The CPU is configured to construct an automaton in accordance with a search expression input thereto, and to perform logical expression evaluations in order of the record sequence number on matching results obtained on a record-by-record basis.
摘要翻译：搜索装置包括加速器和CPU。加速器包括多个搜索核心和调度器。调度器被配置为以记录序列号排序的记录为单位将目标文本分发到搜索核心，并且搜索核心被配置为以并行方式对分布式记录执行自动机匹配。 CPU被配置为根据输入到其中的搜索表达式来构建自动机，并且以记录序列号的顺序对按照记录基础获得的匹配结果进行逻辑表达式评估。

3. 发明授权

US08423499B2 Search device and search method 有权
标题翻译：搜索设备和搜索方法
公开(公告)号：US08423499B2
公开(公告)日：2013-04-16
申请号：US12974877
申请日：2010-12-21
申请人： Yi Ge , Shinichiro Tago
发明人： Yi Ge , Shinichiro Tago
IPC分类号： G06F17/00 , G06F15/00 , G06N7/04 , G06N99/00 , G06E1/00 , G06E3/00 , G06G7/00
CPC分类号： G06F17/30911
摘要： A search device includes an accelerator and a CPU. The accelerator includes a plurality of search cores and a scheduler. The scheduler is configured to distribute target text to the search cores in units of records ordered by record sequence number, and the search cores are configured to perform automaton matching on the distributed records in a parallel fashion. The CPU is configured to construct an automaton in accordance with a search expression input thereto, and to perform logical expression evaluations in order of the record sequence number on matching results obtained on a record-by-record basis.
摘要翻译：搜索装置包括加速器和CPU。加速器包括多个搜索核心和调度器。调度器被配置为以记录序列号排序的记录为单位将目标文本分发到搜索核心，并且搜索核心被配置为以并行方式对分布式记录执行自动机匹配。 CPU被配置为根据输入到其中的搜索表达式来构建自动机，并且以记录序列号的顺序对按照记录基础获得的匹配结果进行逻辑表达式评估。

4. 发明申请

US20090235030A1 Cache system including a plurality of processing units 有权
标题翻译：高速缓存系统包括多个处理单元
公开(公告)号：US20090235030A1
公开(公告)日：2009-09-17
申请号：US12453782
申请日：2009-05-21
申请人： Yi Ge , Shinichiro Tago
发明人： Yi Ge , Shinichiro Tago
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/123 , G06F12/0811 , G06F12/128 , G06F2212/271
摘要： A cache system includes processing units operative to access a main memory device, caches coupled in one-to-one correspondence to the processing units, and a controller coupled to the caches to control data transfer between the caches and data transfer between the main memory and the caches, wherein the controller includes a memory configured to store first information and second information separately for each index, the first information indicating an order of oldness of entries in each one of the caches, and the second information indicating an order of oldness of entries for the plurality of the caches, and a logic circuit configured to select an entry to be evicted and its destination in response to the first and second information when an entry of an index corresponding to an accessed address is to be evicted from a cache corresponding to the processing unit that accesses the main memory device.
摘要翻译：高速缓存系统包括可操作以访问主存储器设备的处理单元，与处理单元一一对应地耦合的高速缓存，以及耦合到高速缓存的控制器，以控制高速缓存之间的数据传输以及主存储器和所述高速缓存，其中所述控制器包括被配置为针对每个索引分别存储第一信息和第二信息的存储器，所述第一信息指示每个所述高速缓存中的条目的旧的顺序，以及所述第二信息指示条目的旧的顺序以及逻辑电路，被配置为当与所访问的地址相对应的索引的条目将从对应于所访问的地址的高速缓存中被逐出时，响应于所述第一和第二信息来选择要被驱逐的条目及其目的地处理单元，其访问主存储器件。

5. 发明授权

US08874879B2 Vector processing circuit, command issuance control method, and processor system 有权
标题翻译：矢量处理电路，命令发布控制方法和处理器系统
公开(公告)号：US08874879B2
公开(公告)日：2014-10-28
申请号：US13279482
申请日：2011-10-24
申请人： Yi Ge , Yoshimasa Takebe , Hiromasa Takahashi
发明人： Yi Ge , Yoshimasa Takebe , Hiromasa Takahashi
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30109 , G06F9/30149 , G06F9/3836
摘要： A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.
摘要翻译：矢量处理电路包括包括多个阵列元素的矢量寄存器文件，命令发布控制电路和多个流水线运算单元。每个流水线运算单元通过多个周期以部分方式，通过一个命令对存储在源表示的数组元素中的数据进行算术处理，并将该结果存储在通过多个周期的一个命令作为目的地表示的数组元素中。当前一个命令的数据字长度大于后续命令的数据字长时，命令发布控制电路根据命令的数据字长度改变数组元素的数据大小，并确定数组元素与在前一个命令的非头循环处理，以及要在后续命令的头循环处理的数组元素。

6. 发明申请

US20120204082A1 DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD 有权
标题翻译：数据总线系统，其编码器/解码器和编码/解码方法
公开(公告)号：US20120204082A1
公开(公告)日：2012-08-09
申请号：US13446565
申请日：2012-04-13
申请人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
发明人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： G06F11/10
摘要： The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme.
摘要翻译：本申请涉及数据总线系统，其编码器/解码器和编码/解码方法。数据总线编码器包括：总线反转编码器，用于通过根据预定的总线反转编码方案对数据执行总线反转编码来产生编码数据和反转指示信息; 虚拟位组生成器，用于根据预定的代码映射将反转指示信息转换为虚拟位组; 以及用于根据预定的错误检查和校正编码方案为虚拟字生成错误校验码的纠错编码器，其中错误校验位的数目大于在预定的错误校验和校正编码方案中至少一个纠错位的数量，虚拟字包括要输出的数据，对应于数据的虚拟位组，以及至少一个填充位，其被配置为由错误校验和校正编码方案所要求的。

7. 发明申请

US20120030543A1 PROTECTION OF APPLICATION IN MEMORY 审中-公开
标题翻译：保护应用程序在内存中
公开(公告)号：US20120030543A1
公开(公告)日：2012-02-02
申请号：US13180713
申请日：2011-07-12
申请人： Yi Ge , Rui Hou , Li Li , Liang Liu
发明人： Yi Ge , Rui Hou , Li Li , Liang Liu
IPC分类号： G06F11/10
CPC分类号： G06F11/1004
摘要： A method, a memory controller and a processor architecture for protecting an application in a memory are disclosed. The application is cached as memory lines according to a size of a cache line. For example, the method comprises: in response to a load access request from a processor, reading from the memory a flagged memory line and an ECC checksum corresponding to the memory line, wherein the flagged memory line is obtained by performing a logic operation on a predetermined bit of the memory line and a flag bit for identifying the memory line; performing an ECC check on the flagged memory line by using the ECC checksum to obtain a value of the flag bit of the memory line; restoring the flagged memory line to the memory line according to the value of the flag bit; and determining whether or not to load the memory line according to the value of the flag bit and the type of the load access request from the processor.
摘要翻译：公开了一种用于保护存储器中的应用的方法，存储器控制器和处理器架构。应用程序根据高速缓存行的大小来缓存为内存行。例如，该方法包括：响应于来自处理器的负载访问请求，从存储器读取标记的存储器线和对应于存储器线的ECC校验和，其中通过对标记的存储器线执行逻辑运算来获得标记的存储器线存储器线的预定位和用于识别存储器线的标志位; 通过使用ECC校验和对所标记的存储器线执行ECC检查以获得存储器线的标志位的值; 根据标志位的值将标记的存储器线恢复到存储器线; 以及根据所述标志位的值和来自所述处理器的所述负载访问请求的类型来确定是否加载所述存储器线。

8. 发明授权

US07814485B2 System and method for adaptive power management based on processor utilization and cache misses 有权
标题翻译：基于处理器利用率和高速缓存未命中的自适应电源管理系统和方法
公开(公告)号：US07814485B2
公开(公告)日：2010-10-12
申请号：US11007098
申请日：2004-12-07
申请人： Bryan C Morgan , Premanand Sakarda , Priya N Vaidya , Yi Ge , Zhou Gao , Swee-chin Pang , Manoj I Thadani , Canhui Yuan
发明人： Bryan C Morgan , Premanand Sakarda , Priya N Vaidya , Yi Ge , Zhou Gao , Swee-chin Pang , Manoj I Thadani , Canhui Yuan
IPC分类号： G06F9/46 , G06F1/00
CPC分类号： G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.
摘要翻译：处理系统可以包括性能监视单元（PMU），机器可访问介质和响应于PMU和机器可访问介质的处理器。在机器可访问介质中编码的指令在由处理器执行时可以至少部分地基于用于处理系统的预定监视策略来确定是否应该收集处理系统的性能细节。该指令可以至少部分地基于从PMU获得的数据来生成处理系统的性能数据。所述指令可以至少部分地基于所述处理系统的性能数据和功率策略简档来确定所述处理系统是否应被重新配置。该指令可以通过使用PMU重新配置处理系统来自动调整处理系统的功耗。描述和要求保护其他实施例。

9. 发明申请

US20090202880A1 ELECTROCHEMICAL MEDIATORS 审中-公开
标题翻译：电化学介质
公开(公告)号：US20090202880A1
公开(公告)日：2009-08-13
申请号：US12263734
申请日：2008-11-03
申请人： Yi Ge , Paula Pizarro De Sousa Brito , Anthony Peter Francis Turner
发明人： Yi Ge , Paula Pizarro De Sousa Brito , Anthony Peter Francis Turner
IPC分类号： H01M8/10 , C25B11/04 , G01N27/26
CPC分类号： G01N33/5438 , C08G83/005 , C08J5/2256 , C08J2300/202
摘要： A redox mediator is a hyperbranched polymer having redox moieties (e.g. ferrocene) incorporated into its structure and/or chemically bonded to its periphery. It is attached to an electrode and assists in transferring electrons between the electrode and a redox enzyme.
摘要翻译：氧化还原介体是具有结合到其结构中和/或化学键合到其周边的氧化还原部分（例如二茂铁）的超支化聚合物。它附着在电极上，有助于在电极和氧化还原酶之间转移电子。

10. 发明申请

US20090178054A1 CONCOMITANCE SCHEDULING COMMENSAL THREADS IN A MULTI-THREADING COMPUTER SYSTEM 有权
标题翻译：在多线程计算机系统中的协调调度通用螺纹
公开(公告)号：US20090178054A1
公开(公告)日：2009-07-09
申请号：US12348933
申请日：2009-01-06
申请人： Ying Chen , Yi Ge , Rui Hou , Liang Liu , Xiao Zhong
发明人： Ying Chen , Yi Ge , Rui Hou , Liang Liu , Xiao Zhong
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/484
摘要： A method and an apparatus for concomitance scheduling a work thread and assistant threads associated with the work thread in a multi-threading processor system. The method includes: searching one or more assistant threads associated with the running of the work thread when preparing to run/schedule the work thread; running the one or more assistant threads that are searched; and running the work thread after all of the one or more assistant threads associated with the running of the work thread have run.
摘要翻译：一种用于在多线程处理器系统中调度工作线程和与工作线程相关联的辅助线程的方法和装置。该方法包括：在准备运行/调度工作线程时，搜索与工作线程的运行相关联的一个或多个辅助线程; 运行所搜索的一个或多个辅助线程; 并且在运行与工作线程的运行相关联的所有一个或多个辅助线程之后运行工作线程。

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