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1. 发明申请

US20070153597A1 Built-in memory current test circuit 有权
标题翻译：内置内存电流测试电路
公开(公告)号：US20070153597A1
公开(公告)日：2007-07-05
申请号：US11481966
申请日：2006-07-07
申请人： Yeong-Jar Chang , Kun-Lun Luo , Jung-Chi Ho , Cheng-Wen Wu , Chin-Jung Su
发明人： Yeong-Jar Chang , Kun-Lun Luo , Jung-Chi Ho , Cheng-Wen Wu , Chin-Jung Su
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/12 , G11C29/12005 , G11C29/50 , G11C2029/5006
摘要： A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.
摘要翻译：公开了一种用于测试芯片上的存储器的内置存储器电流测试电路，其包括内置的自测电路和动态电流产生模块。内置自检电路设置在芯片上，以接收和处理测试信号，并产生控制信号以控制存储器的操作和电流控制代码。也设置在芯片上的动态电流产生模块基于当前控制码产生到存储器中的测试电流。内置存储器电流测试电路中的当前切换时间减少，因此可以执行组合功能和应力测试的集成测试。

2. 发明授权

US07319625B2 Built-in memory current test circuit 有权
标题翻译：内置内存电流测试电路
公开(公告)号：US07319625B2
公开(公告)日：2008-01-15
申请号：US11481966
申请日：2006-07-07
申请人： Yeong-Jar Chang , Kun-Lun Luo , Jung-Chi Ho , Cheng-Wen Wu , Chin-Jung Su
发明人： Yeong-Jar Chang , Kun-Lun Luo , Jung-Chi Ho , Cheng-Wen Wu , Chin-Jung Su
IPC分类号： G11C7/00
CPC分类号： G11C29/12 , G11C29/12005 , G11C29/50 , G11C2029/5006
摘要： A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.
摘要翻译：公开了一种用于测试芯片上的存储器的内置存储器电流测试电路，其包括内置的自测电路和动态电流产生模块。内置自检电路设置在芯片上，以接收和处理测试信号，并产生控制信号以控制存储器的操作和电流控制代码。也设置在芯片上的动态电流产生模块基于当前控制码产生到存储器中的测试电流。内置存储器电流测试电路中的当前切换时间减少，因此可以执行组合功能和应力测试的集成测试。

3. 发明授权

US07228468B2 Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification 有权
标题翻译：在具有综合征鉴定的记忆中建立自我诊断和修复的方法和装置
公开(公告)号：US07228468B2
公开(公告)日：2007-06-05
申请号：US11001345
申请日：2004-11-30
申请人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Yeong-Jar Chang , Kun-Lun Luo , Shen-Tien Lin
发明人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Yeong-Jar Chang , Kun-Lun Luo , Shen-Tien Lin
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/72 , G11C2029/0405 , G11C2029/3602
摘要： The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.
摘要翻译：本发明提供一种存储器建立自诊断和修复的方法和装置，其具有综合征识别。它在测试过程中使用故障模式识别和故障排序格式结构来识别存储器中的故障行，故障列和单个故障字，然后输出故障信息。基于综合信息，应用冗余分析算法来分配修复故障存储单元的备用存储单元。它具有具有增强的故障综合征识别的定序器，具有改进的冗余利用率的内置冗余分析电路，以及在正常访问期间减少定时损失的地址可重新配置电路。本发明减少了自动测试设备中的占用时间和所需的捕获存储空间。它还增加了修复率，并减少了所需的面积开销。

4. 发明申请

US20060064618A1 Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification 有权
标题翻译：在具有综合征鉴定的记忆中建立自我诊断和修复的方法和装置
公开(公告)号：US20060064618A1
公开(公告)日：2006-03-23
申请号：US11001345
申请日：2004-11-30
申请人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Yeong-Jar Chang , Kun-Lun Luo , Shen-Tien Lin
发明人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Yeong-Jar Chang , Kun-Lun Luo , Shen-Tien Lin
IPC分类号： G01R31/28
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/72 , G11C2029/0405 , G11C2029/3602
摘要： The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.
摘要翻译：本发明提供一种存储器建立自诊断和修复的方法和装置，其具有综合征识别。它在测试过程中使用故障模式识别和故障排序格式结构来识别存储器中的故障行，故障列和单个故障字，然后输出故障信息。基于综合信息，应用冗余分析算法来分配修复故障存储单元的备用存储单元。它具有具有增强的故障综合征识别的定序器，具有改进的冗余利用率的内置冗余分析电路，以及在正常访问期间减少定时损失的地址可重构电路。本发明减少了自动测试设备中的占用时间和所需的捕获存储空间。它还增加了修复率，并减少了所需的面积开销。

5. 发明授权

US06937106B2 Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loop 有权
标题翻译：用于压控振荡器和锁相环的内置抖动测量电路
公开(公告)号：US06937106B2
公开(公告)日：2005-08-30
申请号：US10749560
申请日：2004-01-02
申请人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
发明人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
IPC分类号： G01R29/26 , H03L7/06 , G01R23/00
CPC分类号： G01R29/26 , H03L7/06
摘要： A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.
摘要翻译：公开了一种用于VCO（压控振荡器）和PLL（锁相环）的内置抖动测量电路。该电路包括用于分频信号的分频器，用于将分频信号的周期转换为数字值的时间数字转换器（TDC），用于计算分频信号周期的方差的方差计算器，用于计算分割信号的周期的平均值，用于编码和计算分频信号的周期的编码器和计数器，以及作为所有其他分量的控制器的状态控制器。所公开的电路利用要测量的开环电路的输出时钟和用于增加原始信号的抖动的分频器。通过测量闭环电路的带宽，相应地，通过将测量的带宽与来自外推的抖动值相关联来测量开环或闭环电路的输出时钟的抖动。

6. 发明申请

US20060156104A1 Wrapper testing circuits and method thereof for system-on-a-chip 审中-公开
标题翻译：包装机测试电路及其在片上系统的方法
公开(公告)号：US20060156104A1
公开(公告)日：2006-07-13
申请号：US11140745
申请日：2005-06-01
申请人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
发明人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
IPC分类号： G01R31/28
CPC分类号： G01R31/318555
摘要： A wrapper testing circuit and method thereof for System-On-a-Chip is provided for electrical tests of core circuits of an integrated circuit. The testing circuit includes a decoding logic with an encoding table for receiving test signals and delivering control signals in response to the test signals according to the table; a plurality of registers for saving the control signals temporarily and delivering the control signals to the core circuits; a bypass circuit for delivering the test signals; and an instruction register for saving the test signals temporarily and refreshing the data in the registers and the bypass circuits after the decoding logic issues the control signals. The encoding of the control signals is completed in one period. Compared with the serial encoding in the prior art, test time is reduced.
摘要翻译：提供了一种用于片上系统的封装测试电路及其方法，用于集成电路的核心电路的电气测试。测试电路包括具有编码表的解码逻辑，用于接收测试信号并根据该表响应于测试信号传递控制信号; 多个寄存器，用于暂时保存控制信号并将控制信号传送到核心电路; 用于传递测试信号的旁路电路; 以及在解码逻辑发出控制信号之后暂时保存测试信号并刷新寄存器和旁路电路中的数据的指令寄存器。控制信号的编码在一个周期内完成。与现有技术的串行编码相比，测试时间缩短。

7. 发明授权

US07506231B2 Wrapper testing circuits and method thereof for system-on-a-chip 有权
标题翻译：包装机测试电路及其在片上系统的方法
公开(公告)号：US07506231B2
公开(公告)日：2009-03-17
申请号：US11819464
申请日：2007-06-27
申请人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
发明人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G01R31/318555
摘要： A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.
摘要翻译：提供了一种用于至少集成电路的核心电路的电测试的片上系统的封装测试电路及其包装测试方法。控制器输出控制信号和测试信号并接收由核心电路执行的结果信号。包装测试电路包括解码逻辑和多个封装边界寄存器。解码逻辑具有信号解码表，其接收并解码控制信号，然后根据信号解码表发出解码信号。 WBR移位，更新和捕获核心电路的测试信号，以根据解码的信号执行和输出结果信号。与现有技术相比，测试时间缩短。

8. 发明申请

US20050057312A1 Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loop 有权
公开(公告)号：US20050057312A1
公开(公告)日：2005-03-17
申请号：US10749560
申请日：2004-01-02
申请人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
发明人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
IPC分类号： G01R29/26 , H03L7/06 , H03L7/00
CPC分类号： G01R29/26 , H03L7/06
摘要： A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.

9. 发明申请

US20070255986A1 Wrapper testing circuits and method thereof for system-on-a-chip 有权
标题翻译：包装机测试电路及其在片上系统的方法
公开(公告)号：US20070255986A1
公开(公告)日：2007-11-01
申请号：US11819464
申请日：2007-06-27
申请人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
发明人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
IPC分类号： G01R31/28
CPC分类号： G01R31/318555
摘要： A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.
摘要翻译：提供了一种用于至少集成电路的核心电路的电测试的片上系统的封装测试电路及其包装测试方法。控制器输出控制信号和测试信号并接收由核心电路执行的结果信号。包装测试电路包括解码逻辑和多个封装边界寄存器。解码逻辑具有信号解码表，其接收并解码控制信号，然后根据信号解码表发出解码信号。 WBR移位，更新和捕获核心电路的测试信号，以根据解码的信号执行和输出结果信号。与现有技术相比，测试时间缩短。

10. 发明申请

US20070288807A1 Method And Apparatus Of Build-In Self-Diagnosis And Repair In A Memory With Syndrome Identification 有权
标题翻译：建立自诊断和修复记忆与综合征鉴定的方法和装置
公开(公告)号：US20070288807A1
公开(公告)日：2007-12-13
申请号：US11742567
申请日：2007-04-30
申请人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Kun-Lun Luo
发明人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Kun-Lun Luo
IPC分类号： G11C29/12
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： Disclosed is a build-in self-diagnosis and repair method and apparatus in a memory with syndrome identification. It applies a fail-pattern identification and a syndrome-format structure to identify at least one type of faulty syndrome in the memory during a memory testing, then generates and exports fault syndrome information associated with the corresponding faulty syndrome. According to the fault syndrome information, the method applies a redundancy analysis algorithm, allocates spare memory elements and repairs the faulty cells in the memory. The syndrome-format structure respectively applies single-faulty-word-syndrome format, faulty-row-segment-syndrome format, and faulty-column-segment-syndrome format for different faulty syndromes, such as faulty row segments and single faulty words, faulty column segments and single faulty words, all of single faulty words, faulty row segments and faulty column segments, and so on.
摘要翻译：公开了一种在具有综合征识别的记忆中的内置自诊断和修复方法和装置。它在存储器测试期间应用故障模式识别和综合征格式结构来识别存储器中的至少一种类型的故障综合征，然后产生并输出与相应的故障综合征相关的故障综合征信息。根据故障综合信息，该方法应用冗余分析算法，分配备用存储器元件并修复存储器中的故障单元。综合征格式结构分别针对不良故障综合征，如有缺陷的行段和单一故障字，分别应用单故障字综合征格式，故障行段综合征格式和故障列段综合征格式，列段和单个故障单词，所有单个故障字，故障行段和故障列段等。

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