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1. 发明授权

US06514807B1 Method for fabricating semiconductor device applied system on chip 有权
标题翻译：制造半导体器件的芯片应用系统的方法
公开(公告)号：US06514807B1
公开(公告)日：2003-02-04
申请号：US09955779
申请日：2001-09-18
申请人： Yen-hung Yeh , Tso-Hung Fan , Hung-Sui Lin , Shih-Keng Cho , Mu Yi Liu , Kwang Yang Chan , Tao-Cheng Lu
发明人： Yen-hung Yeh , Tso-Hung Fan , Hung-Sui Lin , Shih-Keng Cho , Mu Yi Liu , Kwang Yang Chan , Tao-Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L27/11293 , H01L27/105
摘要： The present invention provides a method for fabricating a semiconductor device that can be applied in system on chip (SOC), comprising: providing a substrate with a memory cell region and a peripheral circuit region; forming a plurality of bit-lines in the memory cell region; forming a first and a second dielectric layers respectively in the memory cell region and the peripheral circuit region; and forming a plurality of gates. Next, a blanket ion implantation step is performed to form a plurality of P type LDDs in the substrate besides the gates in a PMOS device region within the peripheral circuit region, without forming an anti-punch through region in the substrate of the memory cell region. Afterwards, a plurality of spacers are formed, connected to one another. An ion implantation step is performed to form a plurality of P type source/drain regions.
摘要翻译：本发明提供一种可应用于片上系统（SOC）的半导体器件的制造方法，包括：向衬底提供存储单元区域和外围电路区域; 在所述存储单元区域中形成多个位线; 在所述存储单元区域和所述外围电路区域中分别形成第一和第二电介质层; 并形成多个门。接下来，进行覆盖离子注入步骤，以在外围电路区域中的PMOS器件区域中的栅极之外的衬底中形成多个P型LDD，而不在存储单元区域的衬底中形成抗穿通区域。之后，形成多个间隔件，彼此连接。执行离子注入步骤以形成多个P型源极/漏极区域。

2. 发明授权

US06790730B2 Fabrication method for mask read only memory device 有权
标题翻译：掩模只读存储器件的制造方法
公开(公告)号：US06790730B2
公开(公告)日：2004-09-14
申请号：US10156325
申请日：2002-05-24
申请人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
发明人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L27/11253 , H01L21/26586 , H01L27/112
摘要： A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.
摘要翻译：描述了一种用于掩模只读存储器件的制造方法。该方法提供衬底，并且在衬底上形成掺杂导电层。之后，将掺杂的导电层图案化以形成多个棒状掺杂导电层，随后通过热氧化在基板上和棒状导电层上形成电介质层。多个扩散区同时形成在基板中的棒状导电层的下方。在电介质层上进一步形成图案化的导电层。

3. 发明授权

US06706575B2 Method for fabricating a non-volatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US06706575B2
公开(公告)日：2004-03-16
申请号：US10055265
申请日：2002-01-22
申请人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
发明人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/112 , H01L27/11253 , H01L27/115
摘要： A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.
摘要翻译：描述了制造非易失性存储器的方法。提供其上具有条带堆叠结构的基板。然后在衬底旁边的衬底上形成掩埋漏极，并在掩埋漏极上形成绝缘层。在衬底上顺序形成硅层和覆盖层。然后，在垂直于埋地漏极的方向上连续地对盖层，硅层和条带堆叠结构进行图案化，其中条带层叠结构被图案化成多个栅极。衬底氧化物层形成在栅极，衬底和硅层的暴露表面上。此后，除去盖层，并在硅层的暴露表面上形成金属硅化物层。

4. 发明授权

US06587387B1 Device and method for testing mask ROM for bitline to bitline isolation leakage 有权
标题翻译：用于测试屏蔽ROM的位线到位线隔离泄漏的设备和方法
公开(公告)号：US06587387B1
公开(公告)日：2003-07-01
申请号：US10055571
申请日：2002-01-22
申请人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
发明人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
IPC分类号： G11C2900
CPC分类号： G11C29/025 , G11C17/14 , G11C29/02 , G11C2029/5006
摘要： A Mask ROM testing device is described. The Mask ROM testing device comprises a substrate, a plurality of buried bit-lines in the substrate and a plurality of word-lines on the substrate perpendicular to the buried bit-lines. Each buried bit-line has two end portions with a combined length of about 3˜30 &mgr;m and can have an N-type conductivity or a P-type conductivity.
摘要翻译：描述了面罩ROM测试装置。掩模ROM测试装置包括衬底，衬底中的多个掩埋位线和垂直于掩埋位线的衬底上的多个字线。每个埋置的位线具有两个具有约3〜30μm的组合长度的端部，并且可以具有N型导电性或P型导电性。

5. 发明授权

US06838691B2 Chalcogenide memory and method of manufacturing the same 有权
标题翻译：硫族元素记忆及其制造方法
公开(公告)号：US06838691B2
公开(公告)日：2005-01-04
申请号：US10090542
申请日：2002-03-04
申请人： Mu-Yi Liu , Tso-Hung Fan , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Mu-Yi Liu , Tso-Hung Fan , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L27/24 , H01L29/04 , H01L29/06
CPC分类号： H01L27/24
摘要： A method of manufacturing chalcogenide memory in a semiconductor substrate. The method includes the steps of forming a N+ epitaxy layer on the semiconductor substrate; forming a N− epitaxy layer on the N+ epitaxy layer; forming a first STI in the N+ and N− epitaxy layers to isolate a predetermined word line region; forming a second STI in the N− epitaxy layer to isolate a predetermined P+ doped region; forming a dielectric layer on the N− epitaxy layer; patterning the dielectric layer to form a first opening and performing a N+ doping on the N− epitaxy layer via the first opening such that a N+ doped region is formed in the N− epitaxy layer and connected to the N+ epitaxy layer; patterning the dielectric layer to form a second opening and performing a P+ doping on the N− epitaxy layer such that a P+ doped region is formed; forming contact plugs in the first opening and the second opening respectively; and forming an electrode on each contact plug, wherein the electrode includes a lower electrode, a chalcogenide layer and an upper electrode.
摘要翻译：在半导体衬底中制造硫族化物存储器的方法。该方法包括在半导体衬底上形成N +外延层的步骤; 在N +外延层上形成N-外延层; 在N +和N-外延层中形成第一STI以隔离预定的字线区域; 在所述N-外延层中形成第二STI以隔离预定的P +掺杂区; 在所述N-外延层上形成介电层; 图案化介电层以形成第一开口，并且经由第一开口在N外延层上进行N +掺杂，使得N +掺杂区形成在N外延层中并连接到N +外延层; 图案化介电层以形成第二开口并且在N外延层上执行P +掺杂以形成P +掺杂区域; 分别在所述第一开口和所述第二开口中形成接触塞; 以及在每个接触塞上形成电极，其中所述电极包括下电极，硫族化物层和上电极。

6. 发明授权

US06834013B2 Method for programming and erasing non-volatile memory with nitride tunneling layer 有权
标题翻译：用氮化物隧道层编程和擦除非易失性存储器的方法
公开(公告)号：US06834013B2
公开(公告)日：2004-12-21
申请号：US10015414
申请日：2001-12-12
申请人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
发明人： Tso-Hung Fan , Yen-Hung Yeh , Kwang-Yang Chan , Mu-Yi Liu , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/14
摘要： A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.
摘要翻译：描述了用氮化物隧穿层编程和擦除非易失性存储器的方法。非易失性存储器通过向栅极施加第一电压并使衬底接地以接通源极和漏极之间的沟道并且向漏极施加第二电压并且将源接地以感应通道中的电流来编程从而在其中产生热电子。热电子通过氮化物隧穿层注入到非挥发性的电荷捕获层中并被捕获在其中。通过向漏极施加第一正偏压，向栅极施加第二正偏压，并且将源极和衬底接地以在沟道区域中产生热电子空穴来擦除非易失性存储器。热电子空穴通过氮化物隧穿层注入电荷捕获层。

7. 发明授权

US06713821B2 Structure of a mask ROM device 有权
标题翻译：掩模ROM器件的结构
公开(公告)号：US06713821B2
公开(公告)日：2004-03-30
申请号：US10155619
申请日：2002-05-24
申请人： Tso-Hung Fan , Mu-Yi Liu , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Tso-Hung Fan , Mu-Yi Liu , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L31062
CPC分类号： H01L27/1126 , H01L27/112
摘要： A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.
摘要翻译：描述掩模ROM设备。掩模ROM器件包括衬底，栅极，包括第一掺杂区域和第二掺杂区域的双扩散源极/漏极区域，沟道区域，编码区域，电介质层和字线。栅极设置在基板上。双扩散源极/漏极区域位于衬底中的栅极的侧面旁边，其中第二掺杂区域位于衬底中的第一掺杂区域的外围。沟道区位于衬底中的双扩散源极/漏极区之间。编码区域设置在沟道区域和双扩散源极/漏极区域的相交处的衬底中。电介质层设置在双扩散源极/漏极区域的上方，而字线设置在电介质层和栅极之上。

8. 发明授权

US06590266B1 2-bit mask ROM device and fabrication method thereof 有权
标题翻译： 2位掩模ROM器件及其制造方法
公开(公告)号：US06590266B1
公开(公告)日：2003-07-08
申请号：US10064906
申请日：2002-08-28
申请人： Mu-Yi Liu , Tso-Hung Fan , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Mu-Yi Liu , Tso-Hung Fan , Kwang-Yang Chan , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L2994
CPC分类号： H01L27/11266 , H01L27/112
摘要： A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.
摘要翻译：描述2位掩模ROM器件及其制造方法。 2位掩模ROM器件包括衬底; 栅极结构，设置在所述衬底的一部分上; 2位代码区，配置在栅极结构的两侧旁边的基板中; 设置在所述栅极结构的两侧的至少一个间隔物; 掩埋漏极区域，被构造在所述衬底旁边的所述间隔物的两侧; 掺杂区域，配置在掩埋漏极区域和2位码区域之间的衬底中，其中掺杂区域的掺杂剂类型与2位码区域的掺杂区域不同，并且掺杂区域中的掺杂剂浓度更高比在2位代码区域; 绝缘层，设置在所述掩埋漏极区域的上方; 以及沿同一行设置在栅极结构上的字线。

9. 发明授权

US06482706B1 Method to scale down device dimension using spacer to confine buried drain implant 有权
标题翻译：使用间隔器缩小器件尺寸以限制埋漏极植入物的方法
公开(公告)号：US06482706B1
公开(公告)日：2002-11-19
申请号：US10013982
申请日：2001-12-10
申请人： Yen-hung Yeh , Tso-Hung Fan , Mu Yi Liu , Kwang Yang Chan , Tao-Cheng Lu
发明人： Yen-hung Yeh , Tso-Hung Fan , Mu Yi Liu , Kwang Yang Chan , Tao-Cheng Lu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method of scaling down device dimension using spacer to confine the buried drain implant, applicable for forming memory device such as substrate/oxide/nitride/oxide/silicon (SONOS) stacked device or nitride read only memory (NROM) device. A patterned conductive layer is used as a mask for forming a pocket doped region. A spacer is formed on a side-wall of the conductive layer. As the implantation region is confined by the side-wall, a buried drain region formed by drain implantation is reduced. Therefore, the effective channel length is not reduced due to the diffusion of the buried drain region. It is thus advantageous to scale down device dimension.
摘要翻译：一种使用间隔物来缩小器件尺寸以限制掩埋漏极注入的方法，适用于形成诸如衬底/氧化物/氮化物/氧化物/硅（SONOS）堆叠器件或氮化物只读存储器（NROM）器件的存储器件。使用图案化导电层作为形成口袋掺杂区域的掩模。在导电层的侧壁上形成间隔物。当注入区被侧壁限制时，通过漏极注入形成的掩埋漏极区减小。因此，由于埋漏区的扩散，有效沟道长度不会降低。因此有利的是缩小器件尺寸。

10. 发明授权

US06458642B1 Method of fabricating a sonos device 有权
标题翻译：制造声纳装置的方法
公开(公告)号：US06458642B1
公开(公告)日：2002-10-01
申请号：US09990159
申请日：2001-11-20
申请人： Yen-hung Yeh , Tso-Hung Fan , Mu Yi Liu , Kwang Yang Chan , Tao-Cheng Lu
发明人： Yen-hung Yeh , Tso-Hung Fan , Mu Yi Liu , Kwang Yang Chan , Tao-Cheng Lu
IPC分类号： H01L218238
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A method of fabricating a SONOS device, in which a first silicon oxide layer, a trapping layer, and a second silicon oxide layer are formed on the substrate. Then, a mask pattern is formed over the substrate to serve as a mask in the implantation process for forming the buried bit-lines. Afterward, a portion of the mask pattern is removed to increase the gap size of the mask pattern, then a pocket ion implantation is performed to form a pocket doped region at the periphery of the buried bit-line by using the mask pattern as a mask. Subsequently, the mask pattern is removed and a thermal process is conducted using the trapping layer as a mask to form a buried bit-line oxide layer. A word-line is subsequently formed over the substrate.
摘要翻译：一种制造SONOS器件的方法，其中在衬底上形成第一氧化硅层，俘获层和第二氧化硅层。然后，在用于形成掩埋位线的注入工艺中，在衬底上形成掩模图案以用作掩模。之后，去除掩模图案的一部分以增加掩模图案的间隙尺寸，然后通过使用掩模图案作为掩模，进行袋离子注入以在掩埋位线的周围形成凹坑掺杂区域。随后，去除掩模图案，并使用捕获层作为掩模进行热处理，以形成掩埋的位线氧化物层。随后在衬底上形成字线。

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