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1. 发明授权

US08921075B2 Method of manufacturing nanoparticle chain 有权
标题翻译：制造纳米颗粒链的方法
公开(公告)号：US08921075B2
公开(公告)日：2014-12-30
申请号：US13488748
申请日：2012-06-05
申请人： Yen-Pei Lu , Ming-Yu Lin , Yu-Sheng Lai , Yuh-Shyong Yang , Hsuen-Li Chen , Yu-Cheng Ou
发明人： Yen-Pei Lu , Ming-Yu Lin , Yu-Sheng Lai , Yuh-Shyong Yang , Hsuen-Li Chen , Yu-Cheng Ou
IPC分类号： C12P19/34 , C12Q1/68
CPC分类号： C12P19/34 , C12Q1/6834 , C12Q2525/151 , C12Q2525/307 , C12Q2563/155
摘要： A method of manufacturing a nanoparticle chain is disclosed. The method comprises the steps of: providing a single-stranded circular primer with a determined length, and amplifying the single-stranded circular primer into single-stranded DNA nanotemplate by an isothermal nucleotide amplification reaction such that an end of the single-stranded DNA nanotemplate is fixed to a surface of a substrate; and adding a single-stranded DNA probe conjugated with nanoparticle at one end of which, and attaching the single-stranded DNA probe to the corresponding sequence on the single-stranded DNA nanotemplate to form a nanoparticles chain. The method of manufacturing a nanoparticle chain further comprises providing a fluid, and the flowing direction of the fluid controls the aligning direction of the nanoparticle chain. Wherein, the inter-nanoparticle distance of the nanoparticle chain can be adjusted by adjusting a reaction temperature or adding the single-stranded DNA probe without conjugating with nanoparticles.
摘要翻译：公开了一种制造纳米颗粒链的方法。该方法包括以下步骤：提供具有确定长度的单链环状引物，并通过等温核苷酸扩增反应将单链环状引物扩增成单链DNA纳米模板，使得单链DNA纳米模板的末端固定在基板的表面上; 并在其一端加入与纳米颗粒缀合的单链DNA探针，并将单链DNA探针连接到单链DNA纳米模板上的相应序列上以形成纳米颗粒链。制造纳米颗粒链的方法还包括提供流体，流体的流动方向控制纳米颗粒链的排列方向。其中，可以通过调节反应温度或加入单链DNA探针而不与纳米颗粒共轭来调节纳米颗粒链的纳米颗粒间距离。

2. 发明申请

US20130273610A1 Method of Manufacturing Nanoparticle Chain 有权
标题翻译：制造纳米粒子链的方法
公开(公告)号：US20130273610A1
公开(公告)日：2013-10-17
申请号：US13488748
申请日：2012-06-05
申请人： Yen-Pei Lu , Ming-Yu Lin , Yu-Sheng Lai , Yuh-Shyong Yang , Hsuen-Li Chen , Yu-Cheng Ou
发明人： Yen-Pei Lu , Ming-Yu Lin , Yu-Sheng Lai , Yuh-Shyong Yang , Hsuen-Li Chen , Yu-Cheng Ou
IPC分类号： C12P19/34
CPC分类号： C12P19/34 , C12Q1/6834 , C12Q2525/151 , C12Q2525/307 , C12Q2563/155
摘要： A method of manufacturing a nanoparticle chain is disclosed. The method comprises the steps of: providing a single-stranded circular primer with a determined length, and amplifying the single-stranded circular primer into single-stranded DNA nanotemplate by an isothermal nucleotide amplification reaction such that an end of the single-stranded DNA nanotemplate is fixed to a surface of a substrate; and adding a single-stranded DNA probe conjugated with nanoparticle at one end of which, and attaching the single-stranded DNA probe to the corresponding sequence on the single-stranded DNA nanotemplate to form a nanoparticles chain. The method of manufacturing a nanoparticle chain further comprises providing a fluid, and the flowing direction of the fluid controls the aligning direction of the nanoparticle chain. Wherein, the inter-nanoparticle distance of the nanoparticle chain can be adjusted by adjusting a reaction temperature or adding the single-stranded DNA probe without conjugating with nanoparticles.
摘要翻译：公开了一种制造纳米颗粒链的方法。该方法包括以下步骤：提供具有确定长度的单链环状引物，并通过等温核苷酸扩增反应将单链环状引物扩增成单链DNA纳米模板，使得单链DNA纳米模板的末端固定在基板的表面上; 并在其一端加入与纳米颗粒缀合的单链DNA探针，并将单链DNA探针连接到单链DNA纳米模板上的相应序列上以形成纳米颗粒链。制造纳米颗粒链的方法还包括提供流体，流体的流动方向控制纳米颗粒链的排列方向。其中，可以通过调节反应温度或加入单链DNA探针而不与纳米颗粒共轭来调节纳米颗粒链的纳米颗粒间距离。

3. 发明授权

US08773089B2 Regulator capable of rapidly recovering an output voltage and a load current thereof 有权
标题翻译：能够迅速恢复输出电压及其负载电流的调节器
公开(公告)号：US08773089B2
公开(公告)日：2014-07-08
申请号：US13099375
申请日：2011-05-03
申请人： Yu-Sheng Lai , Feng-Chia Chang , Yu-Chou Ke
发明人： Yu-Sheng Lai , Feng-Chia Chang , Yu-Chou Ke
IPC分类号： G05F1/00 , G05F1/563
CPC分类号： G05F1/563
摘要： A regulator includes a first amplifier, a second amplifier, a current control circuit, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, and a feedback circuit. The current control circuit includes a controller and at least one switch, and a second terminal of the first P-type metal-oxide-semiconductor transistor is coupled to a second terminal of the second P-type metal-oxide-semiconductor transistor. The regulator utilizes the controller to turn off the at least one switch during operation of the regulator in a light load mode, and the regulator utilizes the controller to turn on the at least one switch in turn when the regulator changes from the light load mode to a heavy load mode. Thus, the regulator can quickly recover a load current in the heavy load mode.
摘要翻译：调节器包括第一放大器，第二放大器，电流控制电路，第一P型金属氧化物半导体晶体管，第二P型金属氧化物半导体晶体管和反馈电路。电流控制电路包括控制器和至少一个开关，第一P型金属氧化物半导体晶体管的第二端子耦合到第二P型金属氧化物半导体晶体管的第二端子。调节器利用控制器在轻负载模式下操作调节器期间关闭至少一个开关，并且当调节器从轻负载模式改变为轻负载模式时，调节器利用控制器依次打开至少一个开关重负载模式。因此，调节器可以在重负载模式下快速恢复负载电流。

4. 发明申请

US20120190163A1 METHOD FOR MAKING DUAL SILICIDE AND GERMANIDE SEMICONDUCTORS 有权
标题翻译：制备双硅氧烷和锗化物半导体的方法
公开(公告)号：US20120190163A1
公开(公告)日：2012-07-26
申请号：US13107679
申请日：2011-05-13
申请人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
发明人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/7833
摘要： A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.
摘要翻译：制造双硅化物或锗化硅半导体的方法包括提供半导体衬底，形成栅极，形成源极/漏极区域，形成第一硅化物，减少间隔物厚度和形成第二硅化物的步骤。形成栅极包括在半导体衬底上形成绝缘层，并在绝缘层上形成栅极。形成源极/漏极区域包括在与绝缘层相邻的半导体衬底中形成轻掺杂源极/漏极区域，在栅极和轻掺杂源极/漏极区域的一部分上形成间隔物，并且形成重掺杂的源极/漏极区域半导体衬底。第一硅化物形成在轻掺杂和重掺杂的源/漏区的暴露表面上。第二硅化物形成在轻掺杂源极/漏极区域的暴露表面上。第一个锗化物和第二个锗化物可以替代第一个硅化物和第二个硅化物。

5. 发明授权

US07557310B2 System and method for estimating dynamic quantities 失效
标题翻译：用于估计动态量的系统和方法
公开(公告)号：US07557310B2
公开(公告)日：2009-07-07
申请号：US11456864
申请日：2006-07-12
申请人： Yu-Sheng Lai , Je-Wei Liang
发明人： Yu-Sheng Lai , Je-Wei Liang
IPC分类号： G01G15/00 , G01G19/00
CPC分类号： G01G23/3707 , G06Q10/087 , G06Q10/0875
摘要： A system and method for estimating dynamic quantities is provided. The system includes an electronic identification recognition apparatus, a weight measuring apparatus, and a computing apparatus. The electronic identification recognition apparatus can recognize an electronic identification for a corresponding item placed into the system, and the weight measuring apparatus measures a total weight of all items that it carries. The computing apparatus is coupled to the weight measuring apparatus and the electronic identification recognition apparatus, for receiving the total weight, such that the quantity of the item can be estimated and recorded by using the total weights obtained respectively before and after the item is stored or removed and a recognition result from the electronic identification recognition apparatus.
摘要翻译：提供了一种用于估计动态数量的系统和方法。该系统包括电子识别识别装置，重量测量装置和计算装置。电子识别识别装置可以识别放置在系统中的相应物品的电子标识，重量测量装置测量其携带的所有物品的总重量。计算装置耦合到权重测量装置和电子识别识别装置，用于接收总重量，使得可以通过使用分别在项目存储之前和之后获得的总权重来估计和记录该项目的数量，或者去除和电子识别识别装置的识别结果。

6. 发明公开

US20230376090A1 ELECTRONIC DEVICE WITH MOVABLE FOOT PAD 审中-公开
公开(公告)号：US20230376090A1
公开(公告)日：2023-11-23
申请号：US18319495
申请日：2023-05-18
申请人： I-Hsuan Tsai , Chia-Wei Chen , Yu-Sheng Lai , Tzu-Chien Lai
发明人： I-Hsuan Tsai , Chia-Wei Chen , Yu-Sheng Lai , Tzu-Chien Lai
IPC分类号： G06F1/20 , G06F1/16
CPC分类号： G06F1/203 , G06F1/166
摘要： An electronic device with movable foot pad, including a body and a foot pad module, is provided. The body has a bottom surface. The foot pad module includes a first foot pad, at least one second foot pad, and at least one rotating shaft connecting the first and second foot pads. The second foot pad is rotated relative to the first foot pad by the rotating shaft to switch the foot pad module between first and second states. An axial direction of the rotating shaft is inclined relative to the bottom surface. In the first state, the body is supported on the platform by the first and second foot pads. In the second state, the second foot pad is rotated 180 degrees relative to the first foot pad in the axial direction and protrudes from the first foot pad to support the body on the platform by the second foot pad.

7. 发明授权

US08603882B2 Method for making dual silicide and germanide semiconductors 有权
标题翻译：制造双硅化物和锗化硅半导体的方法
公开(公告)号：US08603882B2
公开(公告)日：2013-12-10
申请号：US13107679
申请日：2011-05-13
申请人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
发明人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/7833
摘要： A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.
摘要翻译：制造双硅化物或锗化硅半导体的方法包括提供半导体衬底，形成栅极，形成源极/漏极区域，形成第一硅化物，减少间隔物厚度和形成第二硅化物的步骤。形成栅极包括在半导体衬底上形成绝缘层，并在绝缘层上形成栅极。形成源极/漏极区域包括在与绝缘层相邻的半导体衬底中形成轻掺杂源极/漏极区域，在栅极和轻掺杂源极/漏极区域的一部分上形成间隔物，并且形成重掺杂的源极/漏极区域半导体衬底。第一硅化物形成在轻掺杂和重掺杂的源/漏区的暴露表面上。第二硅化物形成在轻掺杂源极/漏极区域的暴露表面上。第一个锗化物和第二个锗化物可以替代第一个硅化物和第二个硅化物。

8. 发明申请

US20070288237A1 Method And Apparatus For Multimedia Data Management 有权
标题翻译：多媒体数据管理方法与装置
公开(公告)号：US20070288237A1
公开(公告)日：2007-12-13
申请号：US11565628
申请日：2006-12-01
申请人： Chung-Hsien Wu , Yu-Sheng Lai , Chien-Lin Huang , Chia-Hao Kang
发明人： Chung-Hsien Wu , Yu-Sheng Lai , Chien-Lin Huang , Chia-Hao Kang
IPC分类号： G10L15/26
CPC分类号： G10L21/06 , G10L15/26
摘要： A method and an apparatus for multimedia data management are disclosed. The method provides an indexing and retrieval scheme for digital photos with speech annotations based on image-like patterns transformed from the recognized syllable candidates. For annotated spoken content, the recognized n-best syllable candidates are transformed into a sequence of syllable-transformed patterns. Eigen-image analysis is further adopted to extract the significant information to reduce the dimensionality. Vector quantization is applied to quantize the syllable-transformed patterns into feature vectors for indexing. The invention of indexing scheme reduces the dimensionality and noise of data, and achieves better performance of 16.26% for speech annotated photo retrieval.
摘要翻译：公开了一种用于多媒体数据管理的方法和装置。该方法为基于从识别的音节候选者转换的图像样式的语音注释的数字照片提供索引和检索方案。对于有注释的口头内容，识别的最好的音节候选人被转换成音节转换模式的序列。进一步采用特征图像分析提取重要信息以降低维数。矢量量化被应用于将音节变换模式量化为用于索引的特征向量。索引方案的发明降低了数据的维度和噪声，并且对于语音注释的照片检索实现了更高的16.26％的性能。

9. 发明申请

US20120056652A1 DLL circuit with dynamic phase-chasing function and method thereof 有权
标题翻译：具有动态相位跟踪功能的DLL电路及其方法
公开(公告)号：US20120056652A1
公开(公告)日：2012-03-08
申请号：US13024287
申请日：2011-02-09
申请人： Yu-Sheng Lai , Feng-Chia Chang , Chun Shiah
发明人： Yu-Sheng Lai , Feng-Chia Chang , Chun Shiah
IPC分类号： H03L7/08 , H03L7/06
CPC分类号： H03L7/0812 , H03L7/10
摘要： A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.
摘要翻译：动态调整相位追踪速度以提高DLL电路的效率的方法包括检测DLL电路中的输入时钟信号的总体环路延迟，根据总体环路延迟获得最佳因数，并且在锁相周期根据最佳因数除去输入时钟信号的频率和对应于输入时钟信号的反馈时钟信号。

10. 发明申请

US20100073062A1 Voltage Control Oscillator Without Being Affected by Variations of Process and Bias Source 有权
标题翻译：电压控制振荡器不受过程变量和偏置源的影响
公开(公告)号：US20100073062A1
公开(公告)日：2010-03-25
申请号：US12505540
申请日：2009-07-20
申请人： Chun Shiah , Cheng-Nan Chang , Yu-Sheng Lai
发明人： Chun Shiah , Cheng-Nan Chang , Yu-Sheng Lai
IPC分类号： H03K3/00
CPC分类号： H03K3/0315 , H03K2005/00123 , H03K2005/0013 , H03K2005/00202
摘要： A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source.
摘要翻译： VCO包括参考电流模块和时钟信号产生模块。参考电流模块根据参考电压产生参考电流。时钟信号产生模块根据参考电流产生时钟信号。参考电流模块利用负反馈机构将产生的参考电流保持在预定尺寸，而不会随着工艺和偏压源的变化而改变。

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