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1. 发明申请

US20130320408A1 SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130320408A1
公开(公告)日：2013-12-05
申请号：US13483362
申请日：2012-05-30
申请人： Szu-Hung CHEN , Hung-Min Chen , Wen-Fa Wu
发明人： Szu-Hung CHEN , Hung-Min Chen , Wen-Fa Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/265 , H01L21/28518 , H01L29/665
摘要： A semiconductor device comprises a substrate, a metal-semiconductor compound layer and at least one kind of metal dopant. The substrate has a surface. The metal-semiconductor compound layer extends downwards into the substrate from the surface. The metal dopant which is made by one of a group of metal elements with atomic numbers ranging from 57 to 78 or the arbitrary combinations thereof and doped in the metal-semiconductor compound layer and the substrate with at least one peak concentration formed adjacent to the interface of the metal-semiconductor compound layer and the substrate.
摘要翻译：半导体器件包括衬底，金属 - 半导体化合物层和至少一种金属掺杂剂。基板具有表面。金属 - 半导体化合物层从表面向下延伸到基底中。原子序数范围为57〜78的金属元素之一或其任意组合由金属 - 半导体化合物层中掺杂的金属掺杂剂和与界面相邻形成的至少一个峰浓度的基板的金属 - 半导体化合物层和基板。

2. 发明授权

US08302299B2 Method of manufacturing a multilayer printed circuit board with a built-in electronic device 有权
标题翻译：制造具有内置电子设备的多层印刷电路板的方法
公开(公告)号：US08302299B2
公开(公告)日：2012-11-06
申请号：US13013491
申请日：2011-01-25
申请人： Cheng-Hsien Chou , Shun-Yueh Hsu , Kun-Chi Chen , Hung-Min Chen
发明人： Cheng-Hsien Chou , Shun-Yueh Hsu , Kun-Chi Chen , Hung-Min Chen
IPC分类号： H01K3/10
CPC分类号： H05K1/186 , H01L2224/04105 , H01L2224/2518 , H01L2224/92144 , H05K1/185 , H05K1/188 , H05K3/3442 , H05K2201/09063 , H05K2201/10106 , H05K2203/063 , H05K2203/1469 , H05K2203/167 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A method of manufacturing a multilayer printed circuit board of a built-in electronic device provides a substrate having a copper clad laminate and a first dielectric layer. The first dielectric layer is laminated onto the copper clad laminate and has a cavity for accommodating the electronic device. A second dielectric layer is laminated onto the substrate and electronic device to produce a base circuit board with an embedded electronic device. A build-up circuit layer is formed on the base circuit board. The first and second dielectric layers are made of a plastic material.
摘要翻译：制造内置电子器件的多层印刷电路板的方法提供了具有覆铜层压板和第一介电层的基板。将第一介电层层压到覆铜层压板上，并具有用于容纳电子器件的空腔。将第二电介质层层压到基板和电子器件上以产生具有嵌入式电子器件的基极电路板。在基板上形成积层电路层。第一和第二电介质层由塑料材料制成。

3. 发明申请

US20110225816A1 METHOD OF MANUFACTURING A MULTILAYER PRINTED CIRCUIT BOARD WITH A BUILT-IN ELECTRONIC DEVICE 有权
标题翻译：使用内置电子设备制造多层印刷电路板的方法
公开(公告)号：US20110225816A1
公开(公告)日：2011-09-22
申请号：US13013491
申请日：2011-01-25
申请人： Cheng-Hsien CHOU , Shun-Yueh HSU , Kun-Chi CHEN , Hung-Min CHEN
发明人： Cheng-Hsien CHOU , Shun-Yueh HSU , Kun-Chi CHEN , Hung-Min CHEN
IPC分类号： H05K3/00
CPC分类号： H05K1/186 , H01L2224/04105 , H01L2224/2518 , H01L2224/92144 , H05K1/185 , H05K1/188 , H05K3/3442 , H05K2201/09063 , H05K2201/10106 , H05K2203/063 , H05K2203/1469 , H05K2203/167 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A method of manufacturing a multilayer printed circuit board of a built-in electronic device provides a substrate having a copper clad laminate and a first dielectric layer. The first dielectric layer is laminated onto the copper clad laminate and has a cavity for accommodating the electronic device. A second dielectric layer is laminated onto the substrate and electronic device to produce a base circuit board with an embedded electronic device. A build-up circuit layer is formed on the base circuit board. The first and second dielectric layers are made of a plastic material.
摘要翻译：制造内置电子器件的多层印刷电路板的方法提供了具有覆铜层压板和第一介电层的基板。将第一介电层层压到覆铜层压板上，并具有用于容纳电子器件的空腔。将第二电介质层层压到基板和电子器件上以产生具有嵌入式电子器件的基极电路板。在基板上形成积层电路层。第一和第二电介质层由塑料材料制成。

4. 发明授权

US08603882B2 Method for making dual silicide and germanide semiconductors 有权
标题翻译：制造双硅化物和锗化硅半导体的方法
公开(公告)号：US08603882B2
公开(公告)日：2013-12-10
申请号：US13107679
申请日：2011-05-13
申请人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
发明人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/7833
摘要： A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.
摘要翻译：制造双硅化物或锗化硅半导体的方法包括提供半导体衬底，形成栅极，形成源极/漏极区域，形成第一硅化物，减少间隔物厚度和形成第二硅化物的步骤。形成栅极包括在半导体衬底上形成绝缘层，并在绝缘层上形成栅极。形成源极/漏极区域包括在与绝缘层相邻的半导体衬底中形成轻掺杂源极/漏极区域，在栅极和轻掺杂源极/漏极区域的一部分上形成间隔物，并且形成重掺杂的源极/漏极区域半导体衬底。第一硅化物形成在轻掺杂和重掺杂的源/漏区的暴露表面上。第二硅化物形成在轻掺杂源极/漏极区域的暴露表面上。第一个锗化物和第二个锗化物可以替代第一个硅化物和第二个硅化物。

5. 发明申请

US20120190163A1 METHOD FOR MAKING DUAL SILICIDE AND GERMANIDE SEMICONDUCTORS 有权
标题翻译：制备双硅氧烷和锗化物半导体的方法
公开(公告)号：US20120190163A1
公开(公告)日：2012-07-26
申请号：US13107679
申请日：2011-05-13
申请人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
发明人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/7833
摘要： A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.
摘要翻译：制造双硅化物或锗化硅半导体的方法包括提供半导体衬底，形成栅极，形成源极/漏极区域，形成第一硅化物，减少间隔物厚度和形成第二硅化物的步骤。形成栅极包括在半导体衬底上形成绝缘层，并在绝缘层上形成栅极。形成源极/漏极区域包括在与绝缘层相邻的半导体衬底中形成轻掺杂源极/漏极区域，在栅极和轻掺杂源极/漏极区域的一部分上形成间隔物，并且形成重掺杂的源极/漏极区域半导体衬底。第一硅化物形成在轻掺杂和重掺杂的源/漏区的暴露表面上。第二硅化物形成在轻掺杂源极/漏极区域的暴露表面上。第一个锗化物和第二个锗化物可以替代第一个硅化物和第二个硅化物。

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