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1. 发明申请

US20120056652A1 DLL circuit with dynamic phase-chasing function and method thereof 有权
标题翻译：具有动态相位跟踪功能的DLL电路及其方法
公开(公告)号：US20120056652A1
公开(公告)日：2012-03-08
申请号：US13024287
申请日：2011-02-09
申请人： Yu-Sheng Lai , Feng-Chia Chang , Chun Shiah
发明人： Yu-Sheng Lai , Feng-Chia Chang , Chun Shiah
IPC分类号： H03L7/08 , H03L7/06
CPC分类号： H03L7/0812 , H03L7/10
摘要： A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.
摘要翻译：动态调整相位追踪速度以提高DLL电路的效率的方法包括检测DLL电路中的输入时钟信号的总体环路延迟，根据总体环路延迟获得最佳因数，并且在锁相周期根据最佳因数除去输入时钟信号的频率和对应于输入时钟信号的反馈时钟信号。

2. 发明授权

US08384454B2 DLL circuit with dynamic phase-chasing function and method thereof 有权
标题翻译：具有动态相位跟踪功能的DLL电路及其方法
公开(公告)号：US08384454B2
公开(公告)日：2013-02-26
申请号：US13024287
申请日：2011-02-09
申请人： Yu-Sheng Lai , Feng-Chia Chang , Chun Shiah
发明人： Yu-Sheng Lai , Feng-Chia Chang , Chun Shiah
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/10
摘要： A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.
摘要翻译：动态调整相位追踪速度以提高DLL电路的效率的方法包括检测DLL电路中的输入时钟信号的总体环路延迟，根据总体环路延迟获得最佳因数，并且在锁相周期根据最佳因数除去输入时钟信号的频率和对应于输入时钟信号的反馈时钟信号。

3. 发明授权

US08773089B2 Regulator capable of rapidly recovering an output voltage and a load current thereof 有权
标题翻译：能够迅速恢复输出电压及其负载电流的调节器
公开(公告)号：US08773089B2
公开(公告)日：2014-07-08
申请号：US13099375
申请日：2011-05-03
申请人： Yu-Sheng Lai , Feng-Chia Chang , Yu-Chou Ke
发明人： Yu-Sheng Lai , Feng-Chia Chang , Yu-Chou Ke
IPC分类号： G05F1/00 , G05F1/563
CPC分类号： G05F1/563
摘要： A regulator includes a first amplifier, a second amplifier, a current control circuit, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, and a feedback circuit. The current control circuit includes a controller and at least one switch, and a second terminal of the first P-type metal-oxide-semiconductor transistor is coupled to a second terminal of the second P-type metal-oxide-semiconductor transistor. The regulator utilizes the controller to turn off the at least one switch during operation of the regulator in a light load mode, and the regulator utilizes the controller to turn on the at least one switch in turn when the regulator changes from the light load mode to a heavy load mode. Thus, the regulator can quickly recover a load current in the heavy load mode.
摘要翻译：调节器包括第一放大器，第二放大器，电流控制电路，第一P型金属氧化物半导体晶体管，第二P型金属氧化物半导体晶体管和反馈电路。电流控制电路包括控制器和至少一个开关，第一P型金属氧化物半导体晶体管的第二端子耦合到第二P型金属氧化物半导体晶体管的第二端子。调节器利用控制器在轻负载模式下操作调节器期间关闭至少一个开关，并且当调节器从轻负载模式改变为轻负载模式时，调节器利用控制器依次打开至少一个开关重负载模式。因此，调节器可以在重负载模式下快速恢复负载电流。

4. 发明申请

US20120229106A1 REGULATOR 有权
标题翻译：调节器
公开(公告)号：US20120229106A1
公开(公告)日：2012-09-13
申请号：US13099375
申请日：2011-05-03
申请人： Yu-Sheng Lai , Feng-Chia Chang , Yu-Chou Ke
发明人： Yu-Sheng Lai , Feng-Chia Chang , Yu-Chou Ke
IPC分类号： G05F1/10
CPC分类号： G05F1/563
摘要： A regulator includes a first amplifier, a second amplifier, a current control circuit, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, and a feedback circuit. The current control circuit includes a controller and at least one switch, and a second terminal of the first P-type metal-oxide-semiconductor transistor is coupled to a second terminal of the second P-type metal-oxide-semiconductor transistor. The regulator utilizes the controller to turn off the at least one switch during operation of the regulator in a light load mode, and the regulator utilizes the controller to turn on the at least one switch in turn when the regulator changes from the light load mode to a heavy load mode. Thus, the regulator can quickly recover a load current in the heavy load mode.
摘要翻译：调节器包括第一放大器，第二放大器，电流控制电路，第一P型金属氧化物半导体晶体管，第二P型金属氧化物半导体晶体管和反馈电路。电流控制电路包括控制器和至少一个开关，第一P型金属氧化物半导体晶体管的第二端子耦合到第二P型金属氧化物半导体晶体管的第二端子。调节器利用控制器在轻负载模式下操作调节器期间关闭至少一个开关，并且当调节器从轻负载模式改变为轻负载模式时，调节器利用控制器依次打开至少一个开关重负载模式。因此，调节器可以在重负载模式下快速恢复负载电流。

5. 发明申请

US20120169379A1 VOLTAGE HOLD CIRCUIT 有权
标题翻译：电压保持电路
公开(公告)号：US20120169379A1
公开(公告)日：2012-07-05
申请号：US13050969
申请日：2011-03-18
申请人： Yu-Sheng Lai , Feng-Chia Chang
发明人： Yu-Sheng Lai , Feng-Chia Chang
IPC分类号： G11C27/02
CPC分类号： H03L7/10 , H03L7/0812 , H03L2207/08
摘要： A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.
摘要翻译：电压保持电路包括四个开关，运算放大器和电容器。通过打开和关闭开关，运算放大器用作单位增益缓冲器。在正常工作模式下，运算放大器的正输入端耦合到一个节点，运算放大器的输出端耦合到电容器。因此，电容器的电压等于节点的电压。在断电模式下，运算放大器的正输入端耦合到电容器，运算放大器的输出端耦合到节点。因此，节点的电压等于电容器的电压。因此，电压保持电路能够将节点的电压保持在掉电状态。

6. 发明授权

US08330513B2 Voltage hold circuit 有权
标题翻译：电压保持电路
公开(公告)号：US08330513B2
公开(公告)日：2012-12-11
申请号：US13050969
申请日：2011-03-18
申请人： Yu-Sheng Lai , Feng-Chia Chang
发明人： Yu-Sheng Lai , Feng-Chia Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0812 , H03L2207/08
摘要： A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.
摘要翻译：电压保持电路包括四个开关，运算放大器和电容器。通过打开和关闭开关，运算放大器用作单位增益缓冲器。在正常工作模式下，运算放大器的正输入端耦合到一个节点，运算放大器的输出端耦合到电容器。因此，电容器的电压等于节点的电压。在断电模式下，运算放大器的正输入端耦合到电容器，运算放大器的输出端耦合到节点。因此，节点的电压等于电容器的电压。因此，电压保持电路能够将节点的电压保持在掉电状态。

7. 发明申请

US20100073062A1 Voltage Control Oscillator Without Being Affected by Variations of Process and Bias Source 有权
标题翻译：电压控制振荡器不受过程变量和偏置源的影响
公开(公告)号：US20100073062A1
公开(公告)日：2010-03-25
申请号：US12505540
申请日：2009-07-20
申请人： Chun Shiah , Cheng-Nan Chang , Yu-Sheng Lai
发明人： Chun Shiah , Cheng-Nan Chang , Yu-Sheng Lai
IPC分类号： H03K3/00
CPC分类号： H03K3/0315 , H03K2005/00123 , H03K2005/0013 , H03K2005/00202
摘要： A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source.
摘要翻译： VCO包括参考电流模块和时钟信号产生模块。参考电流模块根据参考电压产生参考电流。时钟信号产生模块根据参考电流产生时钟信号。参考电流模块利用负反馈机构将产生的参考电流保持在预定尺寸，而不会随着工艺和偏压源的变化而改变。

8. 发明授权

US07969253B2 VCO with stabilized reference current source module 有权
标题翻译： VCO具有稳定的参考电流源模块
公开(公告)号：US07969253B2
公开(公告)日：2011-06-28
申请号：US12505540
申请日：2009-07-20
申请人： Chun Shiah , Cheng-Nan Chang , Yu-Sheng Lai
发明人： Chun Shiah , Cheng-Nan Chang , Yu-Sheng Lai
IPC分类号： H03B5/00
CPC分类号： H03K3/0315 , H03K2005/00123 , H03K2005/0013 , H03K2005/00202
摘要： A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source.
摘要翻译： VCO包括参考电流模块和时钟信号产生模块。参考电流模块根据参考电压产生参考电流。时钟信号产生模块根据参考电流产生时钟信号。参考电流模块利用负反馈机构将产生的参考电流保持在预定尺寸，而不会随着工艺和偏压源的变化而改变。

9. 发明申请

US20120190163A1 METHOD FOR MAKING DUAL SILICIDE AND GERMANIDE SEMICONDUCTORS 有权
标题翻译：制备双硅氧烷和锗化物半导体的方法
公开(公告)号：US20120190163A1
公开(公告)日：2012-07-26
申请号：US13107679
申请日：2011-05-13
申请人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
发明人： Szu-Hung Chen , Hung-Min Chen , Yu-Sheng Lai , Wen-Fa Wu , Fu-Liang Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/7833
摘要： A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.
摘要翻译：制造双硅化物或锗化硅半导体的方法包括提供半导体衬底，形成栅极，形成源极/漏极区域，形成第一硅化物，减少间隔物厚度和形成第二硅化物的步骤。形成栅极包括在半导体衬底上形成绝缘层，并在绝缘层上形成栅极。形成源极/漏极区域包括在与绝缘层相邻的半导体衬底中形成轻掺杂源极/漏极区域，在栅极和轻掺杂源极/漏极区域的一部分上形成间隔物，并且形成重掺杂的源极/漏极区域半导体衬底。第一硅化物形成在轻掺杂和重掺杂的源/漏区的暴露表面上。第二硅化物形成在轻掺杂源极/漏极区域的暴露表面上。第一个锗化物和第二个锗化物可以替代第一个硅化物和第二个硅化物。

10. 发明授权

US07557310B2 System and method for estimating dynamic quantities 失效
标题翻译：用于估计动态量的系统和方法
公开(公告)号：US07557310B2
公开(公告)日：2009-07-07
申请号：US11456864
申请日：2006-07-12
申请人： Yu-Sheng Lai , Je-Wei Liang
发明人： Yu-Sheng Lai , Je-Wei Liang
IPC分类号： G01G15/00 , G01G19/00
CPC分类号： G01G23/3707 , G06Q10/087 , G06Q10/0875
摘要： A system and method for estimating dynamic quantities is provided. The system includes an electronic identification recognition apparatus, a weight measuring apparatus, and a computing apparatus. The electronic identification recognition apparatus can recognize an electronic identification for a corresponding item placed into the system, and the weight measuring apparatus measures a total weight of all items that it carries. The computing apparatus is coupled to the weight measuring apparatus and the electronic identification recognition apparatus, for receiving the total weight, such that the quantity of the item can be estimated and recorded by using the total weights obtained respectively before and after the item is stored or removed and a recognition result from the electronic identification recognition apparatus.
摘要翻译：提供了一种用于估计动态数量的系统和方法。该系统包括电子识别识别装置，重量测量装置和计算装置。电子识别识别装置可以识别放置在系统中的相应物品的电子标识，重量测量装置测量其携带的所有物品的总重量。计算装置耦合到权重测量装置和电子识别识别装置，用于接收总重量，使得可以通过使用分别在项目存储之前和之后获得的总权重来估计和记录该项目的数量，或者去除和电子识别识别装置的识别结果。

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