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1. 发明授权

US07818356B2 Bitstream buffer manipulation with a SIMD merge instruction 有权
标题翻译：使用SIMD合并指令进行位流缓冲操作
公开(公告)号：US07818356B2
公开(公告)日：2010-10-19
申请号：US10612542
申请日：2003-07-01
申请人： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Young
发明人： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Young
IPC分类号： G06F5/01
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

2. 发明授权

US08510355B2 Bitstream buffer manipulation with a SIMD merge instruction 有权
公开(公告)号：US08510355B2
公开(公告)日：2013-08-13
申请号：US12907843
申请日：2010-10-19
申请人： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
发明人： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
IPC分类号： G06F5/01
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

3. 发明申请

US20110035426A1 Bitstream Buffer Manipulation with a SIMD Merge Instruction 有权
标题翻译：使用SIMD合并指令进行位流缓冲操作
公开(公告)号：US20110035426A1
公开(公告)日：2011-02-10
申请号：US12907843
申请日：2010-10-19
申请人： Yen-Kuang Chen , William W. Macy, JR. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
发明人： Yen-Kuang Chen , William W. Macy, JR. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
IPC分类号： G06F15/00
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

4. 发明授权

US07631025B2 Method and apparatus for rearranging data between multiple registers 有权
标题翻译：用于在多个寄存器之间重新排列数据的方法和装置
公开(公告)号：US07631025B2
公开(公告)日：2009-12-08
申请号：US10612061
申请日：2003-06-30
申请人： Eric L. Debes , William W. Macy, Jr. , Patrice L. Roussel , Yen-Kuang Chen
发明人： Eric L. Debes , William W. Macy, Jr. , Patrice L. Roussel , Yen-Kuang Chen
IPC分类号： G06F5/01
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for rearranging data between multiple registers. The method of one embodiment comprises shuffling first set of packed data from a first source based on a first set of masks to produce a first set of shuffled data. The first set of masks is to include a first plurality of control entries to set designated data element positions in the first set of shuffled data to zero. A second packed data from a second source is shuffled based on a second set of masks to produce a second set of shuffled data. The second set of masks includes a second plurality of control entries to set to zero data element positions in the second set of shuffled data opposite to said designated data element positions in the first set of shuffled data. The first set of shuffled data and said second set of shuffled data are merged together to form a packed data resultant.
摘要翻译：用于在多个寄存器之间重新排列数据的方法，装置和程序装置。一个实施例的方法包括基于第一组掩码从第一源混洗第一组打包数据，以产生第一组混洗数据。第一组掩码是包括第一多个控制条目，以将第一组混洗数据中的指定数据元素位置设置为零。来自第二源的第二打包数据基于第二组掩码进行混洗以产生第二组混洗数据。所述第二组掩码包括第二多个控制条目，以将所述第二组混洗数据中的数据元素位置设置为与所述第一组混洗数据中的所述指定数据元素位置相反的零数据元素位置。第一组混洗数据和所述第二组混洗数据被合并在一起形成打包数据结果。

5. 发明授权

US07739319B2 Method and apparatus for parallel table lookup using SIMD instructions 有权
标题翻译：使用SIMD指令并行表查找的方法和装置
公开(公告)号：US07739319B2
公开(公告)日：2010-06-15
申请号：US10612592
申请日：2003-07-01
申请人： William W. Macy, Jr. , Eric L. Debes , Yen-Kuang Chen , Minerva M. Yeung
发明人： William W. Macy, Jr. , Eric L. Debes , Yen-Kuang Chen , Minerva M. Yeung
IPC分类号： G06F5/01
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing a parallel table lookup using SIMD instructions. The method of one embodiment comprises loading a table having a set of L data elements. A determination of whether the table fits into a single register is made. A data lookup into the table is performed with a packed data shuffle operation if the determination indicates that the table does fit into a single register. The table is divided into a plurality of sections if the table does not fit into a single register. Each of the sections is sized to fit into a single register. A plurality of packed data shuffle operations are executed on the plurality of sections to look up data in the table.
摘要翻译：用于使用SIMD指令执行并行表查找的方法，装置和程序装置。一个实施例的方法包括加载具有一组L个数据元素的表。确定表是否适合单个寄存器。如果确定表示该表适合于单个寄存器，则使用打包数据随机操作来执行对表的数据查找。如果表不适合单个寄存器，则表被分成多个部分。每个部分的大小适合单个寄存器。在多个部分上执行多个打包数据混洗操作以查找表中的数据。

6. 发明授权

US07725521B2 Method and apparatus for computing matrix transformations 有权
标题翻译：用于计算矩阵变换的方法和装置
公开(公告)号：US07725521B2
公开(公告)日：2010-05-25
申请号：US10683186
申请日：2003-10-10
申请人： Yen-Kuang Chen , Eric Q. Li , William W. Macy, Jr. , Minerva M. Yeung
发明人： Yen-Kuang Chen , Eric Q. Li , William W. Macy, Jr. , Minerva M. Yeung
IPC分类号： G06F7/38 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for performing matrix transformations including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two rows of content byte elements are shuffled to generate a first and second packed data respectively including elements of a first two columns and of a second two columns. A third packed data including sums of products is generated from the first packed data and elements from two rows of a matrix by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements from two more rows of the matrix by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed to generate two rows of a product matrix. Elements of the product matrix may be generated in an order that further facilitates a second matrix multiplication.
摘要翻译：一种用于执行矩阵变换的方法和装置，包括对处理器中的打包数据的乘法运算和字节随机操作。在一个实施例中，两行内容字节元素被混洗以生成分别包括前两列和第二两列的元素的第一和第二打包数据。通过乘法加法指令，从第一打包数据和矩阵的两行的元素生成包括产品总和的第三打包数据。通过另一个乘法加法指令，从第二打包数据和来自矩阵的另外两行的元素生成包括乘积和的第四打包数据。然后将第三和第四打包数据的相应的产品总和相加以生成两行乘积矩阵。可以以进一步促进第二矩阵乘法的顺序来生成乘积矩阵的元素。

7. 发明授权

US06816949B2 Method and apparatus for cache management 失效
标题翻译：缓存管理方法和装置
公开(公告)号：US06816949B2
公开(公告)日：2004-11-09
申请号：US10040007
申请日：2002-01-03
申请人： Rainer W. Lienhart , Yen-Kuang Chen , Matthew Holliman , Minerva M. Yeung
发明人： Rainer W. Lienhart , Yen-Kuang Chen , Matthew Holliman , Minerva M. Yeung
IPC分类号： G06F1212
CPC分类号： G06F12/0802 , G06F12/122 , G06F2212/401
摘要： A cache management operation. In one embodiment, a first recall value for a first unit of data is generated, a second recall value for a second unit of data is generated, and the first and second recall values are compared. The unit of data having the higher recall value is stored in a first section of a storage device. The unit of data having the lower recall value is stored in a second section of a storage device. A greater amount of compression is performed on the unit of data having the lower recall value.
摘要翻译：缓存管理操作。在一个实施例中，生成第一数据单元的第一回调值，生成第二数据单元的第二回调值，并比较第一和第二回调值。具有较高回忆值的数据单元被存储在存储设备的第一部分中。具有较低重调用值的数据单元被存储在存储装置的第二部分中。对具有较低回忆值的数据单元执行更大量的压缩。

8. 发明申请

US20050108312A1 Bitstream buffer manipulation with a SIMD merge instruction 有权
标题翻译：使用SIMD合并指令进行位流缓冲操作
公开(公告)号：US20050108312A1
公开(公告)日：2005-05-19
申请号：US10612542
申请日：2003-07-01
申请人： Yen-Kuang Chen , William Macy , Matthew Holliman , Eric Debes , Minerva Young
发明人： Yen-Kuang Chen , William Macy , Matthew Holliman , Eric Debes , Minerva Young
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/315 , G06F9/38 , G06F17/14 , G06F7/38
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

9. 发明授权

US06781589B2 Apparatus and method for extracting and loading data to/from a buffer 有权
标题翻译：用于从缓冲器提取数据并从缓冲器加载数据的装置和方法
公开(公告)号：US06781589B2
公开(公告)日：2004-08-24
申请号：US09948333
申请日：2001-09-06
申请人： William W. Macy , Matthew Holliman , Eric Debes , Yen-Kuang Chen
发明人： William W. Macy , Matthew Holliman , Eric Debes , Yen-Kuang Chen
IPC分类号： G06F1300
CPC分类号： G06F5/065
摘要： An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.
摘要翻译：描述了一种用于提取和从缓冲器加载数据的装置和方法。该方法包括响应于数据访问指令的执行从数据缓冲器中选择数据。数据缓冲器包括多个数据存储设备，其中一个或多个初始地包含所选择的数据。因此，多个数据存储装置形成在位层可寻址的单个地址空间。当所选择的数据从源数据存储装置跨越到数据缓冲器的下一个数据存储装置时，来自源数据存储装置的所选数据的一部分与来自下一数据存储装置的所选数据的剩余部分相连，将所选数据形成为连续单位。最后，一旦形成所选择的数据，所选择的数据被存储在目的地数据存储装置中。

10. 发明申请

US20190043351A1 UBIQUITOUS VISUAL COMPUTING WITNESS 审中-公开
公开(公告)号：US20190043351A1
公开(公告)日：2019-02-07
申请号：US16004299
申请日：2018-06-08
申请人： Shao-Wen Yang , Eve M. Schooler , Maruti Gupta Hyde , Hassnaa Moustafa , Katalin Klara Bartfai-Walcott , Yen-Kuang Chen , Jessica McCarthy , Christina R, Strong , Arun Raghunath , Deepak S. Vembar
发明人： Shao-Wen Yang , Eve M. Schooler , Maruti Gupta Hyde , Hassnaa Moustafa , Katalin Klara Bartfai-Walcott , Yen-Kuang Chen , Jessica McCarthy , Christina R, Strong , Arun Raghunath , Deepak S. Vembar
IPC分类号： G08G1/09 , G06Q50/26 , G11B27/031 , H04N7/18 , G06K9/00
CPC分类号： G08G1/091 , G06F9/4881 , G06F9/505 , G06F21/604 , G06F21/6245 , G06F2209/506 , G06K9/00369 , G06K9/00771 , G06K9/4604 , G06K9/6268 , G06K9/6271 , G06Q50/26 , G08G1/0116 , G08G1/087 , G11B27/031 , H04N7/181
摘要： In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data captured by one or more sensors associated with a first device. Further, the processor comprises circuitry to: access the sensor data captured by the one or more sensors associated with the first device; determine that an incident occurred within a vicinity of the first device; identify a first collection of sensor data associated with the incident, wherein the first collection of sensor data is identified from the sensor data captured by the one or more sensors; preserve, on the memory, the first collection of sensor data associated with the incident; and notify one or more second devices of the incident, wherein the one or more second devices are located within the vicinity of the first device.

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