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1. 发明授权

US08350158B2 Tape wiring substrates and packages including the same 有权
标题翻译：胶带接线基板和包装件
公开(公告)号：US08350158B2
公开(公告)日：2013-01-08
申请号：US12507551
申请日：2009-07-22
申请人： Yechung Chung , Chulwoo Kim , Eunseok Song , Kyoungsei Choi
发明人： Yechung Chung , Chulwoo Kim , Eunseok Song , Kyoungsei Choi
IPC分类号： H05K1/00
CPC分类号： H05K1/0216 , H01L23/4985 , H01L24/17 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H05K1/114 , H05K1/189 , H05K2201/093 , H05K2201/09318 , H05K2201/09663 , H05K2201/09772 , H05K2201/09781 , H05K2201/10674 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, the chip mounting area further including an inner area and a peripheral area, the film further including a lower surface, and vias penetrating the film, the vias being located in the inner area, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film. Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, a lower surface, and vias penetrating the film, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film, the vias being located outside of the chip mounting area. Example embodiments are directed to packages including tape wiring substrates.
摘要翻译：示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域的上表面的膜，所述芯片安装区域还包括内部区域和周边区域，所述膜还包括下表面，以及穿透所述膜的通孔，所述通孔位于所述内部区域中，所述膜的上表面上的上金属层连接到半导体芯片的电极凸块，并且在所述膜的下表面上的下金属层。示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域，下表面和通孔的通孔的上表面的膜，在膜的上表面上的上金属层，并连接到膜的电极凸块半导体芯片以及下部金属层，通孔位于芯片安装区域的外侧。示例性实施例涉及包括带布线基板的封装。

2. 发明申请

US20100038117A1 TAPE WIRING SUBSTRATES AND PACKAGES INCLUDING THE SAME 有权
标题翻译：胶带接线基板和包括它的包装
公开(公告)号：US20100038117A1
公开(公告)日：2010-02-18
申请号：US12507551
申请日：2009-07-22
申请人： Yechung CHUNG , Chulwoo Kim , Eunseok Song , Kyoungsei Choi
发明人： Yechung CHUNG , Chulwoo Kim , Eunseok Song , Kyoungsei Choi
IPC分类号： H05K1/02
CPC分类号： H05K1/0216 , H01L23/4985 , H01L24/17 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H05K1/114 , H05K1/189 , H05K2201/093 , H05K2201/09318 , H05K2201/09663 , H05K2201/09772 , H05K2201/09781 , H05K2201/10674 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, the chip mounting area further including an inner area and a peripheral area, the film further including a lower surface, and vias penetrating the film, the vias being located in the inner area, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film. Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, a lower surface, and vias penetrating the film, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film, the vias being located outside of the chip mounting area. Example embodiments are directed to packages including tape wiring substrates.
摘要翻译：示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域的上表面的膜，所述芯片安装区域还包括内部区域和周边区域，所述膜还包括下表面，以及穿透所述膜的通孔，所述通孔位于所述内部区域中，所述膜的上表面上的上金属层连接到半导体芯片的电极凸块，并且在所述膜的下表面上的下金属层。示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域，下表面和通孔的通孔的上表面的膜，在膜的上表面上的上金属层，并连接到膜的电极凸块半导体芯片以及下部金属层，通孔位于芯片安装区域的外侧。示例性实施例涉及包括带布线基板的封装。

3. 发明授权

US07791377B2 Hierarchical time to digital converter 有权
标题翻译：数字转换器的分层时间
公开(公告)号：US07791377B2
公开(公告)日：2010-09-07
申请号：US12033782
申请日：2008-02-19
申请人： Chulwoo Kim , Minyoung Song , Sunghoon Ahn
发明人： Chulwoo Kim , Minyoung Song , Sunghoon Ahn
IPC分类号： G01R29/00 , H03D3/00 , H03D9/00
CPC分类号： H03K5/159 , G04F10/06 , H03K2005/00286
摘要： A time to digital converter having a hierarchical structure is provided. The time to digital converter includes: a plurality of delay stages for sequentially delaying a first signal for a specific delay time; a plurality of flip-flops for comparing delay signals of the first signal delayed by the delay stages with a second signal, and generating different outputs before and after a phase difference between the delay signals of the first signal and the second signal becomes smaller than a resolution of the phase detector; a selection signal generator for generating a selection signal for selecting a signal most similar to the second signal among the delay signals of the first signal from the outputs of the flip-flops; and a Multiplexer (MUX) for receiving the delay signals of the first signal and the selection signal, and outputting the signal most similar to the second signal among the delay signals of the first signal.
摘要翻译：提供具有层次结构的时间到数字转换器。数字转换器的时间包括：多个延迟级，用于在特定延迟时间内顺序地延迟第一信号; 多个触发器，用于将由延迟级延迟的第一信号的延迟信号与第二信号进行比较，并且在第一信号和第二信号的延迟信号之间的相位差之前和之后产生不同的输出变得小于相位检测器的分辨率; 选择信号发生器，用于从所述触发器的输出产生用于从所述第一信号的延迟信号中选择与所述第二信号最相似的信号的选择信号; 以及用于接收第一信号和选择信号的延迟信号的多路复用器（MUX），并且在第一信号的延迟信号中输出与第二信号最相似的信号。

4. 发明授权

US07579861B2 Impedance-controlled pseudo-open drain output driver circuit and method for driving the same 失效
标题翻译：阻抗控制的开漏输出驱动电路及其驱动方法
公开(公告)号：US07579861B2
公开(公告)日：2009-08-25
申请号：US11906365
申请日：2007-10-01
申请人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
发明人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00384
摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.
摘要翻译：阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有一个预期的阻抗。

5. 发明申请

US20080079458A1 Impedance-controlled pseudo-open drain output driver circuit and method for driving the same 失效
标题翻译：阻抗控制的开漏输出驱动电路及其驱动方法
公开(公告)号：US20080079458A1
公开(公告)日：2008-04-03
申请号：US11906365
申请日：2007-10-01
申请人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
发明人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
IPC分类号： H03K19/0185
CPC分类号： H03K19/00384
摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.
摘要翻译：阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有一个预期的阻抗。

6. 发明授权

US08135104B2 Serial transceiver and communication method used by the serial transceiver 有权
标题翻译：串行收发器使用的串行收发器和通信方式
公开(公告)号：US08135104B2
公开(公告)日：2012-03-13
申请号：US12178347
申请日：2008-07-23
申请人： Chulwoo Kim , Inhwa Jung
发明人： Chulwoo Kim , Inhwa Jung
IPC分类号： H03D3/24
CPC分类号： G06F13/385 , H03L7/0807 , H03L7/087 , H03L7/0891 , H03L7/095 , H03L7/099 , H03L7/10 , H04L7/033 , H04L7/044
摘要： A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.
摘要翻译：高速收发器，不使用外部时钟信号和高速收发器使用的通信方法，其将包括粗码发生器，频率检测器和线性相位检测器的时钟恢复电路应用于接收机，以便解决诸如因为在使用将时钟信息应用于数据的嵌入式时钟方法时，在参考时钟与数据传输期间可能发生的数据之间的偏差以及恢复时钟的抖动。

7. 发明授权

US07698588B2 Circuit and related method for synchronizing data signals to a core clock 有权
标题翻译：用于将数据信号同步到核心时钟的电路和相关方法
公开(公告)号：US07698588B2
公开(公告)日：2010-04-13
申请号：US10439039
申请日：2003-05-15
申请人： David William Boerstler , Chulwoo Kim , Stephen Douglas Weitzel
发明人： David William Boerstler , Chulwoo Kim , Stephen Douglas Weitzel
IPC分类号： G06F1/12 , G06F1/04 , H04L7/10
CPC分类号： H04L7/0012
摘要： The present invention discloses, in one aspect, a synchronizing circuit for synchronizing transmitted data. In one embodiment, the synchronization technique comprises a subsystem configured to compare positive and negative transitions of a core clock signal with positive and negative transitions of a source clock signal to determine a relationship between the transitions of the core clock signal and positions of the negative transitions of the source clock signal. The synchronization circuit also comprises logic circuitry coupled to the subsystem and configured to generate a final sampling signal based on the relationship. In addition, the synchronization circuit comprises a data sampler coupled to the logic circuitry and configured to sample a source data signal synchronized with the source clock signal using the final sampling signal, and to generate a core data signal synchronized with the core clock signal based on the sampling. Also disclosed is a method of synchronizing a data stream, and a data transfer assembly incorporating the synchronization circuit and the method.
摘要翻译：本发明在一个方面公开了一种用于同步发送数据的同步电路。在一个实施例中，同步技术包括子系统，被配置为将核心时钟信号的正和负转换与源时钟信号的正和负转换进行比较，以确定核心时钟信号的转变与负转换位置之间的关系的源时钟信号。同步电路还包括耦合到子系统并被配置为基于该关系产生最终采样信号的逻辑电路。另外，同步电路包括耦合到逻辑电路并被配置为使用最终采样信号对与源时钟信号同步的源数据信号进行采样的数据采样器，并且产生与基于时钟信号同步的核心数据信号抽样。还公开了一种同步数据流的方法，以及包含同步电路和方法的数据传输组件。

8. 发明申请

US20080170616A1 Method and Apparatus for Determining Search Range for Adaptive Motion Vector for Use in Video Encoder 有权
标题翻译：用于确定视频编码器中使用的自适应运动矢量的搜索范围的方法和装置
公开(公告)号：US20080170616A1
公开(公告)日：2008-07-17
申请号：US10552938
申请日：2004-04-08
申请人： Inseong Hwang , Chulwoo Kim , Min-Cheol Hong , Kyoung-Seok In
发明人： Inseong Hwang , Chulwoo Kim , Min-Cheol Hong , Kyoung-Seok In
IPC分类号： H04N7/32
CPC分类号： H04N19/57 , H04N19/105 , H04N19/162 , H04N19/176 , H04N19/61
摘要： The video encoder in accordance with the present invention divides input image signal into macro blocks, estimates motion vectors of each macro block and finally encodes the input image signal. The encoder determines the number of macro blocks adjacent to a current macro block. If the number of adjacent macro blocks is equal to or more than two, the encoder calculates a motion vector of the adjacent macro blocks and selects a macro block that has the largest motion vector. Then it defines a least search area that the current adaptive motion vector can have, and compares the least search area with the motion vector of the largest adjacent macro block, and finally determines the largest value as the search area of the adaptive motion vector. Next, the encoder compares the search area of the adaptive motion vector with the search area of the user-defined motion adaptive vector to thereby determine the least value as the search area of the final adaptive motion vector.
摘要翻译：根据本发明的视频编码器将输入图像信号分成宏块，估计每个宏块的运动矢量，并最终对输入的图像信号进行编码。编码器确定与当前宏块相邻的宏块的数量。如果相邻宏块的数量等于或大于2，则编码器计算相邻宏块的运动矢量，并选择具有最大运动矢量的宏块。然后定义当前自适应运动矢量可以具有的最小搜索区域，并将最小搜索区域与最大相邻宏块的运动矢量进行比较，最后确定最大值作为自适应运动矢量的搜索区域。接下来，编码器将自适应运动矢量的搜索区域与用户定义的运动自适应矢量的搜索区域进行比较，从而确定最小值作为最终自适应运动矢量的搜索区域。

9. 发明授权

US06794903B2 CMOS parallel dynamic logic and speed enhanced static logic 失效
标题翻译： CMOS并行动态逻辑和速度增强静态逻辑
公开(公告)号：US06794903B2
公开(公告)日：2004-09-21
申请号：US09850665
申请日：2001-05-07
申请人： Chulwoo Kim , Sung-Mo Kang
发明人： Chulwoo Kim , Sung-Mo Kang
IPC分类号： H03K19096
CPC分类号： G06F7/508 , H03K19/0963
摘要： A new CMOS dynamic logic family is based on parallel dynamic logic concept, avoiding stacked evaluation transistors. The basic configuration for the logic family is a pair of clock transistors including a NMOS and a PMOS transistor having parallel logic transistors connected between the NMOS and PMOS clock transistors. The parallel-connected transistors have gates for logic inputs and an output originating from one of a commonly connected source or drain. The family may provide NOR, NAND, OR, and AND. The family also includes BUF and INV. The BUF logic gate is realized with opposing NMOS and PMOS and an INV, while the INV uses either a single NMOS or PMOS transistor in place of the parallel-connected transistors. A speed enhanced skewed static logic gate is also provided. The speed enhanced gate uses a plurality of PMOS transistors and a plurality of NMOS transistors matched and joined as a plurality of separate gate inputs. An output from the gate is provided, and the size of PMOS and NMOS transistors are skewed. Positive feedback transistors are connected to the output. A noise suppression transistor is also connected to the output. A precharge transistor connected to the positive feedback transistors is fed from a clock signal from an associated circuit. The speed enhanced skewed state logic gate is preferably used to solve cascading problems, such as those in CD domino or the present parallel dynamic logic, and the speed enhanced static gates may be used instead of clock delay.
摘要翻译：新的CMOS动态逻辑系列基于并行动态逻辑概念，避免了堆叠评估晶体管。逻辑系列的基本配置是一对时钟晶体管，其包括NMOS和PMOS晶体管，其具有连接在NMOS和PMOS时钟晶体管之间的并联逻辑晶体管。并联晶体管具有用于逻辑输入的栅极和源自共同连接的源极或漏极之一的输出。家庭可以提供NOR，NAND，OR和AND。家庭还包括BUF和INV。 BUF逻辑门由相对的NMOS和PMOS和INV实现，而INV使用单个NMOS或PMOS晶体管代替并联晶体管。还提供了速度增强的偏斜静态逻辑门。速度增强栅极使用多个PMOS晶体管和多个NMOS晶体管，这些PMOS晶体管和多个NMOS晶体管作为多个分离的栅极输入进行匹配和连接。提供了来自栅极的输出，并且PMOS和NMOS晶体管的尺寸偏斜。正反馈晶体管连接到输出。噪声抑制晶体管也连接到输出端。连接到正反馈晶体管的预充电晶体管从相关电路的时钟信号馈送。速度增强的偏态状态逻辑门优选地用于解决级联问题，例如CD多米诺骨架或当前并行动态逻辑中的级联问题，并且可以使用速度增强的静态门来代替时钟延迟。

10. 发明授权

US09460937B2 Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages 有权
标题翻译：混合基板，包括其的半导体封装以及用于制造半导体封装的方法
公开(公告)号：US09460937B2
公开(公告)日：2016-10-04
申请号：US14451982
申请日：2014-08-05
申请人： Daewoo Son , Chulwoo Kim
发明人： Daewoo Son , Chulwoo Kim
IPC分类号： H01L21/00 , H01L21/56 , H01L23/36 , H01L23/498 , H01L21/48 , H01L23/31 , H01L23/48 , H01L23/00 , H05K3/46
CPC分类号： H01L25/50 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/76879 , H01L23/3128 , H01L23/36 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/03 , H01L24/09 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/13025 , H01L2224/16225 , H01L2224/16237 , H01L2224/16238 , H01L2224/32145 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06586 , H01L2924/00014 , H01L2924/12042 , H01L2924/12044 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H05K3/4614 , H05K3/4626 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.
摘要翻译：提供了一种混合基板，包括该混合基板的半导体封装以及该半导体封装的制造方法。混合基板可以包括绝缘层和有机层。绝缘层可以包括顶部，与顶部相对的底部，以及具有不同节距的导电图案。有机层可以连接到绝缘层的底部，并且可以包括连接到导电图案的电路图案。导电图案可以包括第一金属图案和第二导电图案。第一金属图案可以具有第一间距，并且可以设置在绝缘层的顶部。第二导电图案可以具有大于第一间距的第二间距，并且可以从第一金属图案延伸以通过绝缘层连接到电路图案。

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