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1. 发明授权

US07791377B2 Hierarchical time to digital converter 有权
标题翻译：数字转换器的分层时间
公开(公告)号：US07791377B2
公开(公告)日：2010-09-07
申请号：US12033782
申请日：2008-02-19
申请人： Chulwoo Kim , Minyoung Song , Sunghoon Ahn
发明人： Chulwoo Kim , Minyoung Song , Sunghoon Ahn
IPC分类号： G01R29/00 , H03D3/00 , H03D9/00
CPC分类号： H03K5/159 , G04F10/06 , H03K2005/00286
摘要： A time to digital converter having a hierarchical structure is provided. The time to digital converter includes: a plurality of delay stages for sequentially delaying a first signal for a specific delay time; a plurality of flip-flops for comparing delay signals of the first signal delayed by the delay stages with a second signal, and generating different outputs before and after a phase difference between the delay signals of the first signal and the second signal becomes smaller than a resolution of the phase detector; a selection signal generator for generating a selection signal for selecting a signal most similar to the second signal among the delay signals of the first signal from the outputs of the flip-flops; and a Multiplexer (MUX) for receiving the delay signals of the first signal and the selection signal, and outputting the signal most similar to the second signal among the delay signals of the first signal.
摘要翻译：提供具有层次结构的时间到数字转换器。数字转换器的时间包括：多个延迟级，用于在特定延迟时间内顺序地延迟第一信号; 多个触发器，用于将由延迟级延迟的第一信号的延迟信号与第二信号进行比较，并且在第一信号和第二信号的延迟信号之间的相位差之前和之后产生不同的输出变得小于相位检测器的分辨率; 选择信号发生器，用于从所述触发器的输出产生用于从所述第一信号的延迟信号中选择与所述第二信号最相似的信号的选择信号; 以及用于接收第一信号和选择信号的延迟信号的多路复用器（MUX），并且在第一信号的延迟信号中输出与第二信号最相似的信号。

2. 发明申请

US20090028274A1 PHASE-DIGITAL CONVERTER HAVING HIERARCHICAL STRUCTURE 有权
标题翻译：具有分层结构的相数转换器
公开(公告)号：US20090028274A1
公开(公告)日：2009-01-29
申请号：US12033782
申请日：2008-02-19
申请人： Chulwoo KIM , Minyoung Song , Sunghoon Ahn
发明人： Chulwoo KIM , Minyoung Song , Sunghoon Ahn
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H03K5/159 , G04F10/06 , H03K2005/00286
摘要： A time to digital converter having a hierarchical structure is provided. The time to digital converter includes: a plurality of delay stages for sequentially delaying a first signal for a specific delay time; a plurality of flip-flops for comparing delay signals of the first signal delayed by the delay stages with a second signal, and generating different outputs before and after a phase difference between the delay signals of the first signal and the second signal becomes smaller than a resolution of the phase detector; a selection signal generator for generating a selection signal for selecting a signal most similar to the second signal among the delay signals of the first signal from the outputs of the flip-flops; and a Multiplexer (MUX) for receiving the delay signals of the first signal and the selection signal, and outputting the signal most similar to the second signal among the delay signals of the first signal.
摘要翻译：提供具有层次结构的时间到数字转换器。数字转换器的时间包括：多个延迟级，用于在特定延迟时间内顺序地延迟第一信号; 多个触发器，用于将由延迟级延迟的第一信号的延迟信号与第二信号进行比较，并且在第一信号和第二信号的延迟信号之间的相位差之前和之后产生不同的输出变得小于相位检测器的分辨率; 选择信号发生器，用于从所述触发器的输出产生用于从所述第一信号的延迟信号中选择与所述第二信号最相似的信号的选择信号; 以及用于接收第一信号和选择信号的延迟信号的多路复用器（MUX），并且在第一信号的延迟信号中输出与第二信号最相似的信号。

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