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1. 发明授权

US06531729B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06531729B2
公开(公告)日：2003-03-11
申请号：US09855773
申请日：2001-05-16
申请人： Akihiko Tsuzumitani , Yasutoshi Okuno , Yoshihiro Mori
发明人： Akihiko Tsuzumitani , Yasutoshi Okuno , Yoshihiro Mori
IPC分类号： H01L2976
CPC分类号： H01L28/60 , H01L27/10852 , H01L28/55
摘要： A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces.
摘要翻译：本发明的半导体器件包括形成在衬底上并含有钌的电极。电极中钌的晶粒具有阶梯面。

2. 发明授权

US06265262B1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06265262B1
公开(公告)日：2001-07-24
申请号：US09587363
申请日：2000-06-02
申请人： Yasutoshi Okuno , Akihiko Tsuzumitani , Yoshihiro Mori
发明人： Yasutoshi Okuno , Akihiko Tsuzumitani , Yoshihiro Mori
IPC分类号： H01L218242
CPC分类号： H01L21/7687 , H01L21/28518 , H01L21/76849 , H01L21/76889 , H01L27/10852 , H01L28/60
摘要： A silicon film is formed within a contact hole formed in a first insulating film on a semiconductor substrate in a manner that an upper portion of the contact hole remains, and a cobalt film is then deposited on the silicon film. Thereafter, a heat treatment is carried out so as to react the silicon film with the cobalt film, thereby forming a cobalt silicide layer in the surface portion of the silicon film. A barrier layer is formed on the cobalt silicide layer so as to completely fill the contact hole, and thus, a plug including the polysilicon film, the cobalt silicide layer and the barrier layer is formed. After a recess is formed in a second insulating film deposited on the first insulating film so as to expose the top surface of the plug, a capacitor bottom electrode, a capacitor dielectric film and a capacitor top electrode are successively formed in the recess.
摘要翻译：在半导体基板上形成在第一绝缘膜上的接触孔内形成硅膜，使得保留接触孔的上部，然后在硅膜上沉积钴膜。此后，进行热处理以使硅膜与钴膜反应，从而在硅膜的表面部分形成钴硅化物层。在硅化钴层上形成阻挡层，以完全填充接触孔，从而形成包括多晶硅膜，硅化钴层和阻挡层的插塞。在沉积在第一绝缘膜上的第二绝缘膜中形成凹部以暴露插头的顶面之后，在凹部中依次形成电容器底部电极，电容器电介质膜和电容器顶部电极。

3. 发明授权

US06436786B1 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US06436786B1
公开(公告)日：2002-08-20
申请号：US09570545
申请日：2000-05-12
申请人： Akihiko Tsuzumitani , Yasutoshi Okuno , Yoshihiro Mori
发明人： Akihiko Tsuzumitani , Yasutoshi Okuno , Yoshihiro Mori
IPC分类号： H01L21331
CPC分类号： H01L28/60 , H01L27/10852 , H01L28/55
摘要： A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces.
摘要翻译：本发明的半导体器件包括形成在衬底上并含有钌的电极。电极中钌的晶粒具有阶梯面。

4. 发明授权

US06884674B2 Method for fabricating a semiconductor device including a capacitance insulating film having a perovskite structure 有权
标题翻译：包括具有钙钛矿结构的电容绝缘膜的半导体器件的制造方法
公开(公告)号：US06884674B2
公开(公告)日：2005-04-26
申请号：US10365502
申请日：2003-02-13
申请人： Akihiko Tsuzumitani , Hisashi Ogawa , Yasutoshi Okuno , Yoshihiro Mori
发明人： Akihiko Tsuzumitani , Hisashi Ogawa , Yasutoshi Okuno , Yoshihiro Mori
IPC分类号： H01L21/02 , H01L21/316 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
CPC分类号： H01L21/02197 , H01L21/02271 , H01L21/31691 , H01L27/10855 , H01L27/11507 , H01L28/55
摘要： A semiconductor device has a capacitance insulating film having a perovskite structure represented by the general formula ABO3 (where each of A and B is a metal element) and first and second electrodes opposed to each other with the capacitance insulating film interposed therebetween. The capacitance insulating film is formed such that the composition of the metal element A or B is higher in the region thereof adjacent the first electrode than in the other region thereof.
摘要翻译：半导体器件具有电容绝缘膜，其具有由通式ABO 3（其中A和B各自为金属元素）表示的钙钛矿结构，并且第一和第二电极彼此相对地具有电容绝缘膜插入其间。电容绝缘膜形成为使得金属元素A或B的组成在与第一电极相邻的区域比其他区域高。

5. 发明授权

US06773979B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06773979B2
公开(公告)日：2004-08-10
申请号：US10032564
申请日：2002-01-02
申请人： Yasutoshi Okuno , Akihiko Tsuzumitani , Yoshihiro Mori
发明人： Yasutoshi Okuno , Akihiko Tsuzumitani , Yoshihiro Mori
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28556 , H01L28/55 , H01L28/91
摘要： The invention provides a method for fabricating a semiconductor device including a concaved capacitor device having a lower electrode, a capacitor dielectric film of a perovskite type high dielectric constant or ferroelectric material formed on the lower electrode and an upper electrode formed on the capacitor dielectric film. In this method, a step of forming a conducting film to be formed into the lower electrode includes sub-steps of forming a lower conducting film by sputtering on walls and a bottom of a recess formed in an insulating film on a substrate; and forming an upper conducting film on the lower conducting film by CVD.
摘要翻译：本发明提供一种制造半导体器件的方法，该半导体器件包括具有下电极的凹陷电容器器件，形成在下电极上的钙钛矿型高介电常数的电容器电介质膜或铁电材料，以及形成在电容器电介质膜上的上电极。在该方法中，形成要形成下电极的导电膜的步骤包括以下步骤：通过溅射在壁上形成下导电膜和形成在基板上的绝缘膜中的凹部的底部; 并通过CVD在下导电膜上形成上导电膜。

6. 发明授权

US06784474B2 Semiconductor memory device and method for fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06784474B2
公开(公告)日：2004-08-31
申请号：US10203430
申请日：2002-08-08
申请人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
发明人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
IPC分类号： H01L2976
CPC分类号： H01L27/10894 , H01L27/10885 , H01L28/55 , H01L28/60 , Y10S257/905 , Y10S257/908
摘要： A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b, over a first interlevel insulating film 18. A conductor sidewall 40 of TiAlN is formed on side faces of hard mask 37, upper barrier metal 36, Pt film 35 and BST film 34. No contact hole is provided on the Pt film 35 constituting an upper electrode 35a. The upper electrode 35a is connected to an upper interconnect (a Cu interconnect 42) via the conductor sidewall 40, dummy lower electrode 33b, dummy cell plug 30 and local interconnect 21b. The Pt film 35 is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film 34a can be prevented.
摘要翻译：作为半导体存储器件的DRAM中的存储单元在第一层间绝缘膜18上设置有连接到位线插头20b和局部互连21b的位线21a。形成TiAlN的导体侧壁40 在硬掩模37，上阻挡金属36，Pt膜35和BST膜34的侧面上。在构成上电极35a的Pt膜35上没有设置接触孔。上电极35a经由导体侧壁40，虚拟下电极33b，虚设电池插塞30和局部互连21b与上互连（铜互连42）连接。 Pt膜35不暴露于还原气氛中，因此可以防止电容绝缘膜34a的特性劣化。

7. 发明授权

US06762445B2 DRAM memory cell with dummy lower electrode for connection between upper electrode and upper layer interconnect 失效
标题翻译：具有用于在上电极和上层互连之间连接的虚拟下电极的DRAM存储单元
公开(公告)号：US06762445B2
公开(公告)日：2004-07-13
申请号：US10196270
申请日：2002-07-17
申请人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
发明人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10894 , H01L28/55
摘要： In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.
摘要翻译：在作为半导体存储器件的DRAM存储单元中，连接到位线插头和局部互连的位线设置在第一层间绝缘膜上。在构成上电极的Pt膜上没有设置接触，并且虚拟下电极与虚拟阻挡金属直接接触。也就是说，上电极通过虚拟下电极，虚拟电池插头和局部互连连接到上层互连（Cu互连）。由于Pt膜不暴露于还原性气氛中，因此可以防止电容绝缘膜的特性劣化。

8. 发明授权

US06916705B2 Semiconductor memory and method for fabricating the same 失效
标题翻译：半导体存储器及其制造方法
公开(公告)号：US06916705B2
公开(公告)日：2005-07-12
申请号：US10656153
申请日：2003-09-08
申请人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
发明人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L27/10894 , H01L28/55 , Y10S438/926
摘要： In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.
摘要翻译：在第一层间绝缘膜上设置DRAM的存储单元，即半导体存储器，连接到位线插头和局部互连的位线。 TiAlN的连接导体膜设置在上阻挡金属的顶面和侧面以及Pt膜和BST膜的侧面上。在用于形成上电极的Pt膜上方没有形成接触，并且上电极通过连接导体膜，虚拟下电极，虚拟电池插头和本地连接到上互连（即Cu互连）互连。由于Pt膜没有暴露于还原气氛中，所以可以防止电容器绝缘膜的特性劣化。

9. 发明授权

US06642564B2 Semiconductor memory and method for fabricating the same 失效
标题翻译：半导体存储器及其制造方法
公开(公告)号：US06642564B2
公开(公告)日：2003-11-04
申请号：US10196229
申请日：2002-07-17
申请人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
发明人： Hisashi Ogawa , Yoshihiro Mori , Akihiko Tsuzumitani
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10894 , H01L28/55 , Y10S438/926
摘要： In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.
摘要翻译：在第一层间绝缘膜上设置DRAM的存储单元，即半导体存储器，连接到位线插头和局部互连的位线。 TiAlN的连接导体膜设置在上阻挡金属的顶面和侧面以及Pt膜和BST膜的侧面上。在用于形成上电极的Pt膜上方没有形成接触，并且上电极通过连接导体膜，虚拟下电极，虚拟电池插头和本地连接到上互连（即Cu互连）互连。由于Pt膜没有暴露于还原气氛中，所以可以防止电容器绝缘膜的特性劣化。

10. 发明授权

US09073566B2 Road surface friction coefficient estimating device 有权
标题翻译：路面摩擦系数估算装置
公开(公告)号：US09073566B2
公开(公告)日：2015-07-07
申请号：US13257698
申请日：2010-03-26
申请人： Toru Takenaka , Hiroyuki Urabe , Yoshihiro Mori
发明人： Toru Takenaka , Hiroyuki Urabe , Yoshihiro Mori
IPC分类号： B62D6/00 , B60T8/172 , B60W40/068
CPC分类号： B62D6/006 , B60T8/172 , B60T2210/12 , B60T2210/22 , B60W40/068
摘要： A road surface friction coefficient estimating device includes a means which finds a first estimated value Mnsp_estm of an external force to be compared (S102 to S116, S118-2), a means which finds a second estimated value Mnsp_sens (S118-1), and a plurality of increasing/decreasing manipulated variable determining means 34_k, each of which determines the increasing/decreasing manipulated variable Δμ_k of the friction coefficient estimated value on the basis of the first estimated value Mnsp_estm and the second estimated value Mnsp_sens, and updates the friction coefficient estimated value according to Δμ_k. The increasing/decreasing manipulated variable determining means 34—1 and 34—2 determine Δμ—1 and Δμ—2 according to a deviation in filtering value between the first estimated value and the second estimated value, and the increasing/decreasing manipulated variable determining means 34—3 determines Δμ—1 according to the deviation between the first estimated value and the second estimated value.
摘要翻译：路面摩擦系数估计装置包括找到要比较的外力的第一估计值Mnsp_estm的装置（S102至S116，S118-2），找到第二估计值Mnsp_sens（S118-1）的装置，以及根据第一估计值Mnsp_estm和第二估计值Mnsp_sens来确定摩擦系数估计值的递增/减少操作变量＆Dgr;μ_k的多个递增/递减操作变量确定装置34_k，并且更新摩擦系数估计值根据＆Dgr;μ_k。上升/下降操作量确定装置34-1和34-2根据第一估计值和第二估计值之间的滤波值的偏差确定＆Dgr;μ-1和＆Dgr;μ-2，并且增加/减小操作变量确定装置34-3根据第一估计值和第二估计值之间的偏差确定＆Dgr;μ-1。

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