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1. 发明授权

US4698652A FET with Fermi level pinning between channel and heavily doped semiconductor gate 失效
标题翻译： FET在通道和重掺杂半导体栅极之间具有费米能级钉扎
公开(公告)号：US4698652A
公开(公告)日：1987-10-06
申请号：US731911
申请日：1985-05-08
申请人： Yasunari Umemoto , Susumu Takahashi , Yuichi Ono
发明人： Yasunari Umemoto , Susumu Takahashi , Yuichi Ono
IPC分类号： H01L29/812 , H01L21/20 , H01L21/31 , H01L21/338 , H01L29/43 , H01L29/49 , H01L29/778 , H01L29/78 , H01L29/80 , H01L29/205
CPC分类号： H01L29/4916 , H01L29/432 , H01L29/4966 , H01L29/802 , H01L29/803 , Y10S148/053 , Y10S148/072 , Y10S148/088 , Y10S148/097
摘要： Herein disclosed is a semiconductor device in which control means for carriers migrating in a first semiconductor includes an interface state layer lying on the first semiconductor and a second conductor layer lying on the interface state layer. The interface state layer has its Fermi level pinned to that of the second semiconductor layer. By thus constructing an FET or the semiconductor device, an inversion or accumulation layer can be easily formed in the interface merely by applying a voltage to the control means.
摘要翻译：这里公开了一种半导体器件，其中在第一半导体中迁移的载流子的控制装置包括位于第一半导体上的界面态层和位于界面状态层上的第二导体层。界面状态层的费米能级固定于第二半导体层的费米能级。通过这样构成FET或半导体装置，仅通过向控制装置施加电压就可以容易地在界面中形成反转或累积层。

2. 发明授权

US4683487A Heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管
公开(公告)号：US4683487A
公开(公告)日：1987-07-28
申请号：US795465
申请日：1985-11-06
申请人： Kiichi Ueyanagi , Susumu Takahashi , Toshiyuki Usagawa , Yasunari Umemoto , Toshihisa Tsukada
发明人： Kiichi Ueyanagi , Susumu Takahashi , Toshiyuki Usagawa , Yasunari Umemoto , Toshihisa Tsukada
IPC分类号： H01L21/331 , H01L29/06 , H01L29/20 , H01L29/417 , H01L29/423 , H01L29/73 , H01L29/737 , H01L29/72
CPC分类号： H01L29/0642 , H01L29/41708 , H01L29/42304 , H01L29/73 , H01L29/7371
摘要： A collector lead-out portion and a base lead-out portion are formed so as to oppose to each other in such a manner that active regions including a collector, a base and an emitter are sandwiched therebetween. The collector lead-out portion and the base lead-out portion are formed by ion implantation or selective epitaxial growth. Thus, a planar type heterojunction bipolar transistor capable of a high density of integration is formed.
摘要翻译：以这样的方式形成集电体引出部分和基极引出部分，以便将包括集电极，基极和发射极的有源区夹在其间的方式彼此相对。集电极引出部分和基极引出部分通过离子注入或选择性外延生长形成。因此，形成了具有高密度集成度的平面型异质结双极晶体管。

3. 发明授权

US4503599A Method of fabricating field effect transistors 失效
标题翻译：制造场效应晶体管的方法
公开(公告)号：US4503599A
公开(公告)日：1985-03-12
申请号：US462014
申请日：1983-01-28
申请人： Kiichi Ueyanagi , Susumu Takahashi , Yasunari Umemoto , Michiharu Nakamura
发明人： Kiichi Ueyanagi , Susumu Takahashi , Yasunari Umemoto , Michiharu Nakamura
IPC分类号： H01L29/78 , H01L21/033 , H01L21/336 , H01L21/338 , H01L29/417 , H01L29/80 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66522 , H01L21/033 , H01L29/66871 , H01L29/80 , H01L29/812
摘要： Herein disclosed is a field effect transistor fabricating method comprising: the step of forming a surface portion of a semiconductor substrate with an impurity region for a channel; the step of forming a first material layer, which has a width substantially equal to that of a gate electrode, in such a position on said semiconductor substrate and is to be formed with said gate electrode, a second material layer, which has a width larger than that of said first material layer, above said first material layer, and source and drain regions by an ion implantation using said first and second material layers thus formed as a mask; the step of forming source and drain electrodes in contact with said source and drain regions; the step of forming a third material layer, which has a selectivity with said first material layer in its etched characteristics, on the semiconductor body thus far prepared by the foregoing steps; the step of forming at least an aperture by removing said first material layer in a state using said third material layer as a mask; and the step of forming said gate electrode in said aperture.
摘要翻译：本文公开了一种场效应晶体管制造方法，包括：形成具有沟道杂质区的半导体衬底的表面部分的步骤; 在所述半导体衬底上形成具有与栅电极的宽度基本相等的第一材料层的步骤，并形成所述栅电极，第二材料层的宽度较大比所述第一材料层的上述第一材料层的上述第一材料层和通过使用由此形成的掩模的所述第一和第二材料层的离子注入的源极和漏极区域; 形成与所述源极和漏极区域接触的源极和漏极的步骤; 在上述步骤制备的半导体本体上形成第三材料层的步骤，该第三材料层具有其蚀刻特性中的所述第一材料层的选择性; 通过以使用所述第三材料层作为掩模的状态除去所述第一材料层来形成至少一个孔的步骤; 以及在所述孔中形成所述栅电极的步骤。

4. 发明授权

US4546540A Self-aligned manufacture of FET 失效
标题翻译： FET的自校准制造
公开(公告)号：US4546540A
公开(公告)日：1985-10-15
申请号：US531709
申请日：1983-09-13
申请人： Kiichi Ueyanagi , Yasunari Umemoto , Susumu Takahashi , Michiharu Nakamura
发明人： Kiichi Ueyanagi , Yasunari Umemoto , Susumu Takahashi , Michiharu Nakamura
IPC分类号： H01L21/265 , H01L21/311 , H01L21/338 , H01L29/417 , H01L29/80 , H01L29/812 , H01L29/48 , H01L21/308
CPC分类号： H01L29/66878 , H01L21/26546 , H01L21/31116 , H01L29/80 , H01L29/812 , Y10S148/083 , Y10S148/143
摘要： This specification discloses a self-aligned manufacturing method of a Schottky gate FET. This method comprises the steps: forming a gate metallic layer on a semiconductor substrate and a mask overhanged on the metallic layer; ion-implanting impurity ions into the semiconductor substrate using the mask to form a source/drain region; depositing an insulator on the gate metallic layer side surface and the other surface below the mask; directionally etching said deposited insulator using the mask to expose the source/drain region; depositing a source/drain electrode using the mask; and removing the mask.
摘要翻译：本说明书公开了肖特基栅极FET的自对准制造方法。该方法包括以下步骤：在半导体衬底上形成栅极金属层和在金属层上突出的掩模; 使用掩模将杂质离子注入到半导体衬底中以形成源/漏区; 在栅极金属层侧表面和掩模下方的另一表面上沉积绝缘体; 使用掩模定向蚀刻所述沉积的绝缘体以暴露源极/漏极区域; 使用掩模沉积源极/漏极; 并取下面罩。

5. 发明授权

US4805005A Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US4805005A
公开(公告)日：1989-02-14
申请号：US783086
申请日：1985-10-02
申请人： Toshiyuki Usagawa , Yasuhiro Shiraki , Yuichi Ono , Susumu Takahashi , Norikazu Hashimoto
发明人： Toshiyuki Usagawa , Yasuhiro Shiraki , Yuichi Ono , Susumu Takahashi , Norikazu Hashimoto
IPC分类号： H01L21/338 , H01L21/8252 , H01L27/095 , H01L29/10 , H01L29/778 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7787 , H01L21/8252 , H01L29/1029 , H01L29/1075 , H01L29/8122
摘要： A semiconductor device and method of manufacturing the same. The device comprises a first n-type semiconductor layer and a second undoped semiconductor layer between which a hetero-junction is formed, and a third p-type embedded semiconductor layer, a gate metal formed without the exposure to air immediately after the third, second and first semiconductor layer are successively formed, and an external electrode connected with the third p-type embedded semiconductor layer, capable of controlling the carriers in the neighborhood of the hetero-junction. This semiconductor device greatly improves the controllability of the threshold voltage thereof, and provides the gate electrodes of good quality.
摘要翻译：一种半导体器件及其制造方法。该器件包括第一n型半导体层和在其之间形成异质结的第二未掺杂半导体层，以及第三p型嵌入式半导体层，在三分之一之后立即形成不暴露于空气的栅极金属，第二并且连续形成第一半导体层，以及与第三p型嵌入式半导体层连接的能够控制异质结附近的载流子的外部电极。该半导体器件极大地提高了其阈值电压的可控性，并且提供质量好的栅电极。

6. 发明授权

US4710787A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4710787A
公开(公告)日：1987-12-01
申请号：US686691
申请日：1984-12-27
申请人： Toshiyuki Usagawa , Yuichi Ono , Susumu Takahashi
发明人： Toshiyuki Usagawa , Yuichi Ono , Susumu Takahashi
IPC分类号： H01L29/812 , H01L21/338 , H01L29/201 , H01L29/205 , H01L29/68 , H01L29/772 , H01L29/778 , H01L29/80 , H01L29/161 , H01L29/06 , H01L29/12 , H01L29/74
CPC分类号： H01L29/7787 , H01L29/7722
摘要： A semiconductor device is provided comprising a control electrode for forming carriers at a junction interface between first and second layers of different materials and for controlling the carriers, a first electrode which is electronically connected to the carriers, and a second electrode region for taking out the carriers in a direction perpendicular to the junction interface. Since the two-dimensional carriers are caused to flow as a current in the direction perpendicular to a plane on which the carriers exist, a great current can be derived as an operating current.
摘要翻译：提供了一种半导体器件，包括用于在不同材料的第一和第二层之间的结界面处形成载流子并用于控制载流子的控制电极，电连接到载体的第一电极和用于取出载体在垂直于结界面的方向上。由于使二维载流子作为与存在载流子的平面垂直的方向的电流流动，所以能够导出大的电流作为工作电流。

7. 发明授权

US08648896B2 Stereoscopic optical system, and optical apparatus for stereoscopic measurement, stereoscopic measurement apparatus and stereoscopic observation apparatus each using the same 有权
标题翻译：立体光学系统和用于立体测量的光学装置，立体测量装置和立体观察装置
公开(公告)号：US08648896B2
公开(公告)日：2014-02-11
申请号：US12653928
申请日：2009-12-17
申请人： Susumu Takahashi
发明人： Susumu Takahashi
IPC分类号： H04N7/18
CPC分类号： G02B23/2415 , A61B1/00193 , A61B1/042
摘要： A stereoscopic optical system includes, at a distal end of an insertion part of an endoscope, a two-path forming optical system for forming two paths of rays involving a parallax, an image forming optical system for forming images out of light travelling along the respective paths of rays in the two-path forming optical system onto a common region, and an image sensor arranged at an image forming position of the image forming optical system. The stereoscopic optical system is further provided with a time-division path switching means that is capable of switching between the two paths of rays in a time-division manner so that only light coming from either one of the two paths of rays formed by the two-path forming optical system enters the image forming optical system.
摘要翻译：立体光学系统在内窥镜的插入部的前端包括用于形成涉及视差的两条光线路的双路形成光学系统，用于形成沿着相应的光线行进的光的图像的成像光学系统将双路形成光学系统中的光线路径映射到公共区域，以及布置在图像形成光学系统的图像形成位置处的图像传感器。立体光学系统还具有时分路径切换装置，该时分路径切换装置能够以时分方式切换两条光线之间的路径，使得只有来自由两个光线形成的两条光线中的任一条光线路径形成光学系统进入成像光学系统。

8. 发明授权

US08547424B2 Endoscope system and lens unit 有权
标题翻译：内窥镜系统和镜头单元
公开(公告)号：US08547424B2
公开(公告)日：2013-10-01
申请号：US12254479
申请日：2008-10-20
申请人： Hiroshi Ishii , Seiji Iwasaki , Masahiro Kawauchi , Hideaki Ishihara , Susumu Takahashi , Shinichi Nakamura , Azusa Noguchi , Hideyasu Takato , Tsutomu Sasamoto
发明人： Hiroshi Ishii , Seiji Iwasaki , Masahiro Kawauchi , Hideaki Ishihara , Susumu Takahashi , Shinichi Nakamura , Azusa Noguchi , Hideyasu Takato , Tsutomu Sasamoto
IPC分类号： A61B1/06 , A61B1/04
CPC分类号： G02B23/26 , A61B1/00096 , A61B1/00186 , A61B1/043 , A61B1/045 , A61B1/063 , A61B1/0638 , A61B1/0646 , A61B5/0071 , A61B5/0084 , G02B23/2438 , G02B23/2469 , G03B9/02 , G03B15/05 , G03B2215/0564 , G03B2215/0575
摘要： An endoscope system has a light source apparatus and an endoscope including an illumination optical system and an objective optical system. At least the objective optical system of the endoscope is provided with an adjustable diaphragm, and in a light path in one of the light source apparatus, the illumination optical system, and the objective optical system, an insertable/retractable filter for observation for special light is provided. The adjustable diaphragm performs a closing operation or an opening operation only when the filter for observation for special light is inserted into the light path.
摘要翻译：内窥镜系统具有包括照明光学系统和物镜光学系统的光源装置和内窥镜。至少内窥镜的物镜光学系统设置有可调节光阑，并且在光源装置，照明光学系统和物镜光学系统之一中的光路中，用于观察特殊光的可插入/可缩回过滤器被提供。仅当用于观察特殊光的过滤器插入光路中时，可调节膜片才执行关闭操作或打开操作。

9. 发明授权

US08422327B2 Semiconductor device having nonvolatile memory element and manufacturing method thereof 有权
标题翻译：具有非易失性存储元件的半导体器件及其制造方法
公开(公告)号：US08422327B2
公开(公告)日：2013-04-16
申请号：US12801124
申请日：2010-05-24
申请人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
发明人： Kazuhiro Teramoto , Hiroki Fujisawa , Susumu Takahashi
IPC分类号： G11C17/18
CPC分类号： G11C29/02 , G11C17/165 , G11C29/027 , G11C29/785 , G11C29/846
摘要： To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.
摘要翻译：为了提供一种包括高电平或低电平的一对反熔丝元件的半导体器件，OR电路为至少一个反熔丝元件处于高电平的情况下输出不同的逻辑信息，以及两个的反熔丝元件为低电平，异或电路输出逻辑状态彼此不同的情况下的不同的逻辑信息以及彼此相同的情况。

10. 发明申请

US20110240095A1 Light reuse sheet, solar battery module, and light source module 审中-公开
标题翻译：光再利用片，太阳能电池模块和光源模块
公开(公告)号：US20110240095A1
公开(公告)日：2011-10-06
申请号：US12998677
申请日：2009-11-19
申请人： Luis Manuel Murillo-Mora , Hideaki Honma , Kohei Moronaga , Susumu Takahashi
发明人： Luis Manuel Murillo-Mora , Hideaki Honma , Kohei Moronaga , Susumu Takahashi
IPC分类号： H01L31/0232 , H01J1/62 , G02B5/08
CPC分类号： H01L31/056 , H01L31/0547 , H01L33/60 , Y02E10/52
摘要： A light reuse sheet includes a reflective surface having an uneven configuration, the reflective surface in order to reflect light in a specific direction so as to cause light to be incident to a solar battery cell, the light being incident to a solar battery module, or in order to exit light in a specific direction by reflecting the light, the light being emitted from a light emitting element of a light source module. The reflective surface satisfies the following formula where a length in a horizontal direction of a solar battery cell or a light emitting element is represented by Lx; a length in a vertical direction of a solar battery cell or a light emitting element is represented by Ly; an angle formed between a direction of an uneven configuration of the reflective surface and an edge in a horizontal direction of the solar battery cell or the light emitting element is represented by φ; and maximum width of light which passes between adjacent solar battery cells and which is reflected by a light reuse sheet and is incident to a light receiving face of a solar battery cell or maximum width of light which is not emitted from a light emitting element in a specific direction and which exits in a specific direction by reflecting the light at a light reuse sheet is represented by A.  f  φ = 0 = Ly · cos   φ - Lx · sin   φ - A  ( cos 2  φ - sin 2   φ ) ( Formula   1 )
摘要翻译：光再利用片材包括具有不均匀构造的反射表面，反射表面以反射特定方向的光，以使光入射到太阳能电池单元，该光入射到太阳能电池模块，或为了通过反射光而在特定方向上退出光，光从光源模块的发光元件发射。反射面满足下式，其中太阳能电池单元或发光元件的水平方向上的长度由Lx表示; 太阳能电池单元或发光元件的垂直方向的长度由Ly表示; 在太阳能电池单元或发光元件的反射表面的不均匀构造的方向与水平方向的边缘之间形成的角度由＆phgr; 和相邻的太阳能电池单元之间通过并由光再利用片材反射并入射到太阳能电池单元的光接收面的光的最大宽度或不从发光元件发射的最大宽度的光特定方向，通过将光反射在光再利用片材上而沿特定方向退出。 = 0 = Ly·cosθ＆phgr - sin;; - 公式（公式1）

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