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1. 发明授权

US07953962B2 Multiprocessor system and control method thereof 有权
标题翻译：多处理器系统及其控制方法
公开(公告)号：US07953962B2
公开(公告)日：2011-05-31
申请号：US12585620
申请日：2009-09-18
申请人： Yasuki Nakamura , Takahisa Suzuki , Makiko Ito , Hideo Miyake
发明人： Yasuki Nakamura , Takahisa Suzuki , Makiko Ito , Hideo Miyake
IPC分类号： G06F9/54
CPC分类号： G06F9/54
摘要： A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information.
摘要翻译：根据实施例的多处理器系统包括多个处理器，执行控制单元，用于控制多个处理器的处理和多个处理器之间的数据传输; 以及内部数据存储单元，用于存储指示数据传送状态的数据相关信息。如果在先前的数据传送被注册执行之后处理器的处理的控制流程是固定的，并且需要与之前的数据传送相同的目的地的另一数据传送，则执行控制单元基于数据依赖信息来取消先前的数据传送。

2. 发明授权

US08510529B2 Method for generating program and method for operating system 失效
标题翻译：用于生成操作系统的程序和方法的方法
公开(公告)号：US08510529B2
公开(公告)日：2013-08-13
申请号：US12888614
申请日：2010-09-23
申请人： Takahisa Suzuki , Hiromasa Yamauchi , Hideo Miyake , Makiko Ito
发明人： Takahisa Suzuki , Hiromasa Yamauchi , Hideo Miyake , Makiko Ito
IPC分类号： G06F12/00
CPC分类号： G06F9/445 , G06F9/44557
摘要： An information processing apparatus sequentially selects a function whose execution frequency is high as a selected function that is to be stored in an internal memory, in a source program having a hierarchy structure. The information processing apparatus allocates the selected function to a memory area of the internal memory, allocates a function that is not the selected function and is called from the selected function to an area close to the memory area of the internal memory, and generates an internal load module. The information processing apparatus allocates a remaining function to an external memory coupled to a processor and generates an external load module. Then, a program executed by the processor having the internal memory is generated.
摘要翻译：在具有层次结构的源程序中，信息处理装置顺序选择执行频率高的功能作为要存储在内部存储器中的选择功能。信息处理装置将所选择的功能分配给内部存储器的存储区域，分配不是所选功能的功能，并且从所选择的功能调用到靠近内部存储器的存储区域的区域，并且生成内部加载模块。信息处理装置将剩余的功能分配给耦合到处理器的外部存储器，并生成外部负载模块。然后，生成由具有内部存储器的处理器执行的程序。

3. 发明申请

US20090019259A1 MULTIPROCESSING METHOD AND MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：多处理方法和多处理器系统
公开(公告)号：US20090019259A1
公开(公告)日：2009-01-15
申请号：US12235209
申请日：2008-09-22
申请人： Takahisa SUZUKI , Makiko Ito , Hideo Miyake
发明人： Takahisa SUZUKI , Makiko Ito , Hideo Miyake
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/5038
摘要： A multiprocessing method and a multiprocessor system capable of reducing time lost due to sequential waiting when procedures (program units) having dependencies are executed in which an order of execution of a plurality of program units in a sequential execution program and dependencies of the plurality of program units are registered, the execution states of the plurality of program units are managed based on the registered dependencies, executable program units are determined, and are assigned to server processors sequentially and executed are disclosed.
摘要翻译：一种多处理方法和多处理器系统，其能够在顺序执行程序中执行多个程序单元的执行顺序和多个程序的依赖性时执行具有依赖关系的程序（程序单元）时由于顺序等待而减少时间损失注册单元，基于注册的依赖关系管理多个程序单元的执行状态，确定可执行程序单元，并且依次分配给服务器处理器并执行。

4. 发明授权

US06868472B1 Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory 失效
标题翻译：控制和寻址作为随机地址存储器以增加对主存储器的访问速度的高速缓冲存储器的方法
公开(公告)号：US06868472B1
公开(公告)日：2005-03-15
申请号：US09671117
申请日：2000-09-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0802 , G06F2212/2515
摘要： In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.
摘要翻译：在本发明的高速缓冲存储器控制方法和计算机中，高速缓存存储器连接到主存储器并被分成多个高速缓存块，并且锁定/解锁信号被提供给高速缓冲存储器以设置替换抑制禁止将至少一个高速缓存块替换为主存储器的至少一个缓存块的状态，或者重置至少一个高速缓冲存储器时钟的替换禁止状态，使得更换高速缓存中的至少一个阻塞到主内存是允许的。通过使用高速缓冲存储器的其余高速缓冲存储器（除了至少一个高速缓存块之外）来执行读取或写入主存储器，使得当通过锁定/解锁信号设置替换禁止状态时，在主存储器的读取或写入期间禁止将至少一个缓存块替换到主存储器。

5. 发明授权

US08181171B2 Method and apparatus for analyzing large scale program and generation of code from degenerated program dependence graph 有权
标题翻译：用于从退化程序依赖图中分析大规模程序和代码生成的方法和装置
公开(公告)号：US08181171B2
公开(公告)日：2012-05-15
申请号：US12191623
申请日：2008-08-14
申请人： Makiko Ito , Hideo Miyake , Atsuhiro Suga
发明人： Makiko Ito , Hideo Miyake , Atsuhiro Suga
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F11/3604
摘要： A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.
摘要翻译：通过使用包括表示语句和控制的依赖关系的多个依赖元素的程序分析信息，语句和控件被包括在程序中，可以发现可逆收缩的依赖元素组。接下来，通过收合找到的依赖元素组来生成依赖元素被收缩的程序依赖图。通过依赖元素的收缩减少程序依赖图的顶点数和边数，从而可以生成具有粗略粒度的程序依赖图。结果，可以减少诸如程序的并行处理的优化处理所需的计算量（计算时间）。也就是说，通过生成具有可逆性的合同程序依赖图，可以在实际的时间内实现大规模软件的分析和优化。

6. 发明申请

US20090007087A1 PROGRAM ANALYZING METHOD, PROGRAM ANALYZING APPARATUS AND PROGRAM ANALYZING PROGRAM 有权
标题翻译：程序分析方法，程序分析装置和程序分析程序
公开(公告)号：US20090007087A1
公开(公告)日：2009-01-01
申请号：US12191623
申请日：2008-08-14
申请人： Makiko Ito , Hideo Miyake , Atsuhiro Suga
发明人： Makiko Ito , Hideo Miyake , Atsuhiro Suga
IPC分类号： G06F9/45
CPC分类号： G06F11/3604
摘要： A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.
摘要翻译：通过使用包括表示语句和控制的依赖关系的多个依赖元素的程序分析信息，语句和控件被包括在程序中，可以发现可逆收缩的依赖元素组。接下来，通过收合找到的依赖元素组来生成依赖元素被收缩的程序依赖图。通过依赖元素的收缩减少程序依赖图的顶点数和边数，从而可以生成具有粗略粒度的程序依赖图。结果，可以减少诸如程序的并行处理的优化处理所需的计算量（计算时间）。也就是说，通过生成具有可逆性的合同程序依赖图，可以在实际的时间内实现大规模软件的分析和优化。

7. 发明授权

US07581090B2 Interrupt control apparatus and method 有权
标题翻译：中断控制装置及方法
公开(公告)号：US07581090B2
公开(公告)日：2009-08-25
申请号：US10692800
申请日：2003-10-27
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F13/24
摘要： When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.
摘要翻译：当正常中断发生时，在正常中断之前的处理器操作的数据被保存在正常的返回地址寄存器（452），正常的先前状态寄存器（453）和正常因子寄存器（454）中。当发生中断中断时，中断中断前的处理器操作数据保存在另一个中断返回地址寄存器（455）中。因此，即使在正常中断的中断禁止期间，中断也可能发生。此外，当发生中断中断时，中断中断状态被设置在标志寄存器（456）中。通过参考标志寄存器（456）执行中断返回指令，可以准确地恢复中断中断前或正常中断前的操作数据。

8. 发明申请

US20080215859A1 Computer with high-speed context switching 审中-公开
标题翻译：具有高速上下文切换的计算机
公开(公告)号：US20080215859A1
公开(公告)日：2008-09-04
申请号：US12073042
申请日：2008-02-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
IPC分类号： G06F9/312 , G06F9/302
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/461 , G06F9/5016 , G06F2207/5353 , Y02D10/22
摘要： A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.
摘要翻译：以时分方式执行多个程序的并行处理的计算机包括划分为多个区域的硬件资源，记录识别第一程序的识别信息的撤离单元，以及排除存储在所述多个区域的区域中的信息如果该区域是执行第二程序所必需的并被用于执行第一程序的区域，以及恢复单元，其在第二程序停止时基于识别信息将该撤离信息恢复到该区域，或者结束。

9. 发明授权

US07376820B2 Information processing unit, and exception processing method for specific application-purpose operation instruction 有权
标题翻译：信息处理单元和特殊应用目的操作指令的异常处理方法
公开(公告)号：US07376820B2
公开(公告)日：2008-05-20
申请号：US09741802
申请日：2000-12-22
申请人： Michihide Kimura , Atsuhiro Suga , Hideo Miyake , Satoshi Imai , Yasuki Nakamura
发明人： Michihide Kimura , Atsuhiro Suga , Hideo Miyake , Satoshi Imai , Yasuki Nakamura
IPC分类号： G06F9/44 , G06F9/54
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3879
摘要： In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.
摘要翻译：在处理器核心中，在控制部分中提供不指定功能规格的操作指令和用于处理特定应用目的操作指令的单元。该单元的结构可以基于灵活的管道结构进行更改，并为每个应用领域单独设计。在处理器核心中还设置有从上述单元的指令发出到可以利用结果的延迟的寄存器，以防止输出端口的争用。规定与发布上述单元的指令的间隔的约束有关的延迟的另一个寄存器也被提供在处理器核心中，以便防止具有前面指令的资源的争用。

10. 发明授权

US07401204B1 Parallel Processor efficiently executing variable instruction word 有权
标题翻译：并行处理器有效执行可变指令字
公开(公告)号：US07401204B1
公开(公告)日：2008-07-15
申请号：US09654527
申请日：2000-09-01
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
IPC分类号： G06F15/00
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3853
摘要： A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.
摘要翻译：并行处理器对包含在由指令定界信息定界的多个指令字中的每个指令字中的一个或多个基本指令执行高效的并行处理。处理器包括：多个指令执行单元，并行地执行根据相应的所提供的基本指令的处理; 指令读取单元根据指令定界信息逐个取出指令字; 以及指令发布单元，其识别并且根据其选择包含在由指令获取单元获取的每个指令字中的每个基本指令给相应的指令执行单元以执行基本指令。

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