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1. 发明申请

US20080220580A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080220580A1
公开(公告)日：2008-09-11
申请号：US12122717
申请日：2008-05-18
申请人： Kunihiko KATO , Masami KOKETSU , Shigeya TOYOKAWA , Keiichi YOSHIZUMI , Hideki YASUOKA , Yasuhiro TAKEDA
发明人： Kunihiko KATO , Masami KOKETSU , Shigeya TOYOKAWA , Keiichi YOSHIZUMI , Hideki YASUOKA , Yasuhiro TAKEDA
IPC分类号： H01L21/8236
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823878 , H01L27/0629 , H01L28/40
摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.
摘要翻译：提供一种制造半导体集成电路器件的方法，该半导体集成电路器件在相同的衬底上具有高击穿电压MISFET和低击穿电压MISFET。预先形成元件隔离沟槽，使得其宽度大于用作低击穿电压的栅电极的多晶硅膜的厚度，栅绝缘膜的厚度和处理中的对准余量之和在与栅电极的延伸方向正交的方向上的栅电极大于不与栅电极重叠的平面区域中的多晶硅膜的厚度。可以减少半导体集成电路器件的制造步骤的数量。

2. 发明申请

US20120187520A1 Semiconductor Device Comprising A Schottky Barrier Diode 有权
标题翻译：包括肖特基势垒二极管的半导体器件
公开(公告)号：US20120187520A1
公开(公告)日：2012-07-26
申请号：US13438190
申请日：2012-04-03
申请人： Kunihiko KATO , Hideki YASUOKA , Masatoshi TAYA , Masami KOKETSU
发明人： Kunihiko KATO , Hideki YASUOKA , Masatoshi TAYA , Masami KOKETSU
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/0692 , H01L29/417
摘要： The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
摘要翻译：本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。阳极导体膜和n型阴极区彼此肖特基耦合。

3. 发明申请

US20120326262A1 Semiconductor Integrated Circuit Device and A Method of Manufacturing the Same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20120326262A1
公开(公告)日：2012-12-27
申请号：US13371015
申请日：2012-02-10
申请人： Kunihiko KATO , Shigeya TOYOKAWA , Kozo WATANABE , Masatoshi TAYA
发明人： Kunihiko KATO , Shigeya TOYOKAWA , Kozo WATANABE , Masatoshi TAYA
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L21/823857 , H01L21/823878 , H01L27/0629 , H01L29/0619 , H01L29/417 , H01L2924/0002 , H01L2924/00
摘要： To reduce size of a finished product by reducing the number of externally embedded parts, embedding of a Schottky barrier diode relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. It is general practice to densely arrange a number of contact electrodes in a matrix over a Schottky junction region. A sputter etching process to the surface of a silicide layer at the bottom of each contact hole is performed before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.
摘要翻译：为了通过减少外部嵌入部件的数量来减小成品的尺寸，已经追求了在半导体集成电路器件中嵌入相当大的电流量的肖特基势垒二极管。通常的做法是在肖特基结区域上的矩阵中密集布置多个接触电极。在沉积阻挡金属层之前，对每个接触孔底部的硅化物层的表面进行溅射蚀刻工艺。然而，在其中将电极布置在肖特基结区上方的结构中，肖特基势垒二极管中的反向泄漏电流由于溅射蚀刻量的变化而变化。本发明是一种具有肖特基势垒二极管的半导体集成电路器件，其中接触电极布置在与周边隔离区接触的保护环上。

4. 发明申请

US20090243027A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US20090243027A1
公开(公告)日：2009-10-01
申请号：US12399957
申请日：2009-03-08
申请人： Kunihiko KATO , Shigeya TOYOKAWA , Kozo WATANABE , Masatoshi TAYA
发明人： Kunihiko KATO , Shigeya TOYOKAWA , Kozo WATANABE , Masatoshi TAYA
IPC分类号： H01L29/872 , H01L21/22
CPC分类号： H01L29/872 , H01L21/823857 , H01L21/823878 , H01L27/0629 , H01L29/0619 , H01L29/417 , H01L2924/0002 , H01L2924/00
摘要： To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.
摘要翻译：为了通过减少外部嵌入部件的数量来进一步减小成品的尺寸，已经追求了在半导体集成电路器件中嵌入的电流量相对较大的肖特基势垒二极管。在这种情况下，通常的做法是在肖特基结区域上将矩阵中的大量接触电极密集布置。在阻挡金属层沉积之前，已经广泛地执行相对于每个接触孔底部的硅化物层的表面的溅射蚀刻工艺。然而，在其中将电极布置在肖特基结区上方的结构中，肖特基势垒二极管中的反向泄漏电流由于溅射蚀刻量的变化而变化。本发明是一种具有肖特基势垒二极管的半导体集成电路器件，其中接触电极布置在与周边隔离区接触的保护环上。

5. 发明申请

US20110199851A1 MEMORY CONTROLLER, SEMICONDUCTOR STORAGE DEVICE, AND MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER AND THE SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：存储器控制器，半导体存储器件和包括存储器控制器和半导体存储器件的存储器系统
公开(公告)号：US20110199851A1
公开(公告)日：2011-08-18
申请号：US13028862
申请日：2011-02-16
申请人： Kunihiko KATO , Toru ISHIKAWA
发明人： Kunihiko KATO , Toru ISHIKAWA
IPC分类号： G11C8/18
CPC分类号： G11C5/148 , G06F13/1689 , G11C7/04 , G11C7/1066 , G11C7/1093 , Y02D10/14
摘要： A memory system includes a clock generation circuit, a memory device, and a controller. The memory device includes output circuits and a temperature sensor, the output circuits configured to output data at an output timing obtained based on a clock signal supplied from the clock generation circuit. The controller includes input circuits that receive the data outputted from the memory device at an input timing obtained based on a clock signal supplied from the clock generation circuit and a correction value setting circuit that adjusts the input timing based on a temperature value from the temperature sensor.
摘要翻译：存储器系统包括时钟产生电路，存储器件和控制器。所述存储装置包括输出电路和温度传感器，所述输出电路经配置以基于从所述时钟发生电路提供的时钟信号获得的输出定时输出数据。该控制器包括输入电路，该输入电路基于从时钟发生电路提供的时钟信号获得的输入定时接收从存储器件输出的数据，以及校正值设置电路，其基于来自温度传感器的温度值调节输入定时。

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