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1. 发明申请

US20130075864A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130075864A1
公开(公告)日：2013-03-28
申请号：US13612194
申请日：2012-09-12
申请人： Seiji OTAKE , Yasuhiro TAKEDA , Yuta MIYAMOTO
发明人： Seiji OTAKE , Yasuhiro TAKEDA , Yuta MIYAMOTO
IPC分类号： H01L27/06
CPC分类号： H01L27/0259
摘要： An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.
摘要翻译： ESD保护元件由包括具有适当杂质浓度的N +型掩埋层和P +型掩埋层的PN结二极管和使用连接到P +型扩散层的P +型绘图层的寄生PNP双极晶体管形成，作为作为基极的N型外延层和作为集电体的P型半导体基板。 P +型埋层与阳极连接，P +型扩散层与P +型扩散层连接并围绕P +型扩散层的N +型扩散层与阴极电极连接。当向阴极施加大的正静电时，寄生PNP双极晶体管导通以流过大的放电电流。

2. 发明申请

US20130075865A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130075865A1
公开(公告)日：2013-03-28
申请号：US13612224
申请日：2012-09-12
申请人： Seiji OTAKE , Yasuhiro TAKEDA , Yuta MIYAMOTO
发明人： Seiji OTAKE , Yasuhiro TAKEDA , Yuta MIYAMOTO
IPC分类号： H01L27/06
CPC分类号： H01L27/0259
摘要： An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.
摘要翻译： ESD保护元件由包括具有适当杂质浓度的N +型掩埋层和第一P +型掩埋层的PN结二极管和使用连接到P +型扩散层的第二P +型掩埋层的寄生PNP双极晶体管形成作为发射极，以N型外延层为基底，第一P +型埋层作为集电体。第一P +型埋层与阳极连接，P +型扩散层和围绕P +型扩散层的N +型扩散层与阴极电极连接。当向阴极施加大的正静电时，并且寄生PNP双极晶体管导通以流过大的放电电流。

3. 发明申请

US20090261410A1 DMOS TRANSISTOR 有权
标题翻译： DMOS晶体管
公开(公告)号：US20090261410A1
公开(公告)日：2009-10-22
申请号：US12425592
申请日：2009-04-17
申请人： Seiji OTAKE , Shuichi Kikuchi , Yasuhiro Takeda , Kenichi Maki
发明人： Seiji OTAKE , Shuichi Kikuchi , Yasuhiro Takeda , Kenichi Maki
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/41758 , H01L29/41775 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66689
摘要： This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.
摘要翻译：本发明提供一种DMOS晶体管，其具有降低的导通电阻并且防止其相对静电放电的强度劣化。 DMOS晶体管的源极层的边缘部分被设置为从栅电极的内角部分退出。硅化物层被构造为不从源极层的边缘部分延伸出来。也就是说，尽管在源极层的表面上形成硅化物层，但是在源极层和栅电极的内角部之间露出的体层的一部分的表面上不形成硅化物层。结果，由于电流几乎均匀地流过整个DMOS晶体管而没有会聚，所以可以提高抵抗静电放电的强度。

4. 发明申请

US20120112240A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120112240A1
公开(公告)日：2012-05-10
申请号：US13286832
申请日：2011-11-01
申请人： Yasuhiro TAKEDA , Seiji OTAKE
发明人： Yasuhiro TAKEDA , Seiji OTAKE
IPC分类号： H01L29/739
CPC分类号： H01L29/7816 , H01L29/0873 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7823 , H01L29/7835
摘要： An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
摘要翻译：由形成有N +型漏极层等的N型外延层构成的N型层由从N型外延层的前表面延伸到N +型掩埋层的P型漏极隔离层包围。在由P型漏极隔离层包围的N型外延层构成的N型层和从N型层的前表面延伸到内部的P型元件隔离层形成P型集电极层。因此，形成使用第一导电型漏极隔离层作为发射极，第二导电型N型层作为基极的集电极层作为集电极的寄生双极型晶体管，以将浪涌电流流入地线。

5. 发明申请

US20090278200A1 TRANSISTOR, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：晶体管，半导体器件及其制造方法
公开(公告)号：US20090278200A1
公开(公告)日：2009-11-12
申请号：US12434128
申请日：2009-05-01
申请人： Yasuhiro TAKEDA , Seiji OTAKE , Kazunori FUJITA
发明人： Yasuhiro TAKEDA , Seiji OTAKE , Kazunori FUJITA
IPC分类号： H01L29/78 , H01L21/20 , H01L21/22
CPC分类号： H01L21/823456 , H01L21/2815 , H01L21/823412 , H01L21/823487 , H01L29/0653 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66734 , H01L29/7809 , H01L29/7813
摘要： An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer. The trench gate type transistor is formed in the first region of the semiconductor layer and the planar type transistor is formed in the second region of the semiconductor layer.
摘要翻译：同时优化沟槽栅型晶体管的导通电阻和平面型晶体管的耐电压。半导体层的第一和第二区域中的每一个分别通过在半导体衬底的第一和第二区域中的每一个上外延生长而形成。在半导体衬底的第一区域和半导体层的第一区域之间形成第一掩埋层，而在半导体衬底的第二区域和半导体层的第二区域之间形成第二掩埋层。第一掩埋层由N +型第一杂质掺杂层和延伸超过第一杂质掺杂层的N型第二杂质掺杂层形成。第二掩埋层仅由N +型杂质掺杂层形成。在半导体层的第一区域中，杂质从半导体层的表面扩散到半导体层中以形成N型第三杂质掺杂层。沟槽栅型晶体管形成在半导体层的第一区域中，并且平面型晶体管形成在半导体层的第二区域中。

6. 发明申请

US20090014790A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及半导体器件制造方法
公开(公告)号：US20090014790A1
公开(公告)日：2009-01-15
申请号：US12167764
申请日：2008-07-03
申请人： Seiji OTAKE , Yasuhiro TAKEDA , Kenichi MAKI
发明人： Seiji OTAKE , Yasuhiro TAKEDA , Kenichi MAKI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0623 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7809
摘要： A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.
摘要翻译：一种半导体器件包括：栅极，其形成在沟槽中，绝缘膜具有与源极区域和基极区域相邻的第一侧面;以及第二导电型第一杂质区域，其形成在所述沟槽的第二侧面附近，凹槽和存在于底部区域下方的漏区的引出部分，以便向下延伸超过凹槽的下端。

7. 发明申请

US20090250759A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090250759A1
公开(公告)日：2009-10-08
申请号：US12419150
申请日：2009-04-06
申请人： Seiji OTAKE
发明人： Seiji OTAKE
IPC分类号： H01L27/06
CPC分类号： H01L27/0629
摘要： A breakdown voltage of a clamp diode can be reduced while a leakage current is suppressed. A P− type diffusion layer is formed in a surface of an N− type semiconductor layer. An N+ type diffusion layer is formed in a surface of the P− type diffusion layer. A P+ type diffusion layer is formed adjacent the N+ type diffusion layer in the surface of the P− type diffusion layer. An N+ type diffusion layer is formed adjacent the P− type diffusion layer in the surface of the N− type semiconductor layer. There is formed a cathode electrode, which is electrically connected with the N+ type diffusion layer through a contact hole formed in an insulation film on the N+ type diffusion layer. There is formed a wiring (an anode electrode) connecting between the P+ type diffusion layer and the N+ type diffusion layer through a contact hole formed in the insulation film on the P+ type diffusion layer and a contact hole formed in the insulation film on the N+ type diffusion layer.
摘要翻译：可以减小钳位二极管的击穿电压，同时抑制漏电流。在N-型半导体层的表面形成有P-型扩散层。在P型扩散层的表面形成N +型扩散层。在P型扩散层的表面中与N +型扩散层相邻形成P +型扩散层。在N型半导体层的表面中与P-型扩散层相邻地形成N +型扩散层。形成阴极，其通过形成在N +型扩散层的绝缘膜上的接触孔与N +型扩散层电连接。通过形成在P +型扩散层上的绝缘膜上的接触孔和形成在N +型扩散层上的绝缘膜上的接触孔，形成在P +型扩散层和N +型扩散层之间连接的布线（阳极）型扩散层。

8. 发明申请

US20110204952A1 CURRENT DETECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：电流检测电路和半导体集成电路
公开(公告)号：US20110204952A1
公开(公告)日：2011-08-25
申请号：US13032357
申请日：2011-02-22
申请人： Seiji OTAKE
发明人： Seiji OTAKE
IPC分类号： H03L5/00
CPC分类号： G01R19/0092
摘要： The invention provides a current detection circuit for a transistor, that does not influence a current flowing through the transistor, and minimizes a power loss, an increase of the pattern area and so on. A current detection circuit includes a wiring connected to a MOS transistor and forming a current path of a current of the MOS transistor, a current detection MOS transistor of which the gate is connected to the wiring, that flows a current corresponding to the potential of the gate, and a current detector detecting a current flowing through the current detection MOS transistor. The current detection circuit is configured including a load resistor connected to the current detection MOS transistor and a voltage detection circuit detecting a drain voltage of the current detection MOS transistor.
摘要翻译：本发明提供了一种用于晶体管的电流检测电路，其不影响流过晶体管的电流，并且使功率损耗最小化，图案区域的增加等。电流检测电路包括连接到MOS晶体管并形成MOS晶体管的电流的电流路径的布线，栅极连接到布线的电流检测MOS晶体管，其流过与所述MOS晶体管的电位相对应的电流栅极和检测流过电流检测MOS晶体管的电流的电流检测器。电流检测电路被配置为包括连接到电流检测MOS晶体管的负载电阻器和检测电流检测用MOS晶体管的漏极电压的电压检测电路。

9. 发明申请

US20100207197A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100207197A1
公开(公告)日：2010-08-19
申请号：US12707734
申请日：2010-02-18
申请人： Seiji OTAKE
发明人： Seiji OTAKE
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0626 , H01L29/0696 , H01L29/0873 , H01L29/0878 , H01L29/66689 , H01L29/7821
摘要： In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented.
摘要翻译：在根据本发明的半导体器件中，作为漏极区的N型扩散层形成P型扩散层和N型扩散层作为漏极引线区。 P型扩散层设置在MOS晶体管的源极区域和漏极区域之间。当向漏极施加正的ESD浪涌时，引起寄生晶体管的导通电流流动，这种结构允许寄生晶体管的导通电流通过流过外延层的深部的路径。因此，可防止MOS晶体管的热击穿。

10. 发明申请

US20120299114A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120299114A1
公开(公告)日：2012-11-29
申请号：US13478954
申请日：2012-05-23
申请人： Seiji OTAKE
发明人： Seiji OTAKE
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66272 , H01L29/7322
摘要： The invention is directed to a semiconductor device which is manufactured by a BiCMOS process in which a process of manufacturing a V-NPN transistor is rationalized. Furthermore, the hFE of the transistor is adjusted to a large value. An N type base width control layer is formed being in contact with a bottom portion of a P type base region under an N+ type emitter region. The N type base width control layer shallows a portion of the P type base region under the N+ type emitter region partially. The P type base region is formed by using a process of forming a P type well region, and the N type base width control layer is formed by using a process of forming an N type well region, thereby achieving the process rationalization.
摘要翻译：本发明涉及通过BiCMOS工艺制造的半导体器件，其中制造V-NPN晶体管的工艺合理化。此外，将晶体管的hFE调节到较大的值。形成与N +型发射极区域下的P型基极区域的底部接触的N型基极宽度控制层。 N型基极宽度控制层部分地在N +型发射极区域的浅层部分P型基极区域。通过使用形成P型阱区的工艺形成P型基区，并且通过使用形成N型阱区的工艺形成N型基极宽度控制层，从而实现工艺合理化。

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