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    • 3. 发明授权
    • Elastic store memory circuit
    • 弹性存储器电路
    • US5444658A
    • 1995-08-22
    • US206221
    • 1994-03-07
    • Naoyuki IzawaYasuhiro AsoYoshihiro UchidaSatoshi Kakuma
    • Naoyuki IzawaYasuhiro AsoYoshihiro UchidaSatoshi Kakuma
    • H04J3/06H04L7/00G11C7/00
    • H04J3/0626
    • An elastic store memory circuit includes first and second elastic store memories. Each of the first and second elastic store memories generates a phase comparison signal when a phase difference between a write timing and a read timing is within a predetermined phase range. The elastic store memory circuit also includes a selector which selects either the input data read out from the first elastic store memory or the input data read out from the second elastic store memory, and a slip signal generator for generating a slip signal on the basis of a write reset timing at which the first and second elastic store memories are reset, a read reset timing at which the first and second elastic store memories are reset, and the phase comparison signal. The slip signal indicates which one of the write reset timing and the read reset timing precedes the other one.
    • 弹性存储存储器电路包括第一和第二弹性存储器存储器。 当写入定时和读取定时之间的相位差在预定相位范围内时,第一和第二弹性存储存储器中的每一个产生相位比较信号。 弹性存储器电路还包括选择器,其选择从第一弹性存储存储器读出的输入数据或从第二弹性存储器读出的输入数据,以及滑移信号发生器,用于基于 复位第一和第二弹性存储器的写入复位定时,复位第一和第二弹性存储器的读取复位定时以及相位比较信号。 打印信号指示写入复位定时和读取复位定时中哪一个先于另一个。
    • 6. 发明授权
    • Apparatus for testing ATM channels
    • ATM通道测试装置
    • US5313453A
    • 1994-05-17
    • US854888
    • 1992-03-20
    • Yoshihiro UchidaSatoshi KakumaNaoyuki IzawaYasuhiro AsoShuji YoshimuraMasami Murayama
    • Yoshihiro UchidaSatoshi KakumaNaoyuki IzawaYasuhiro AsoShuji YoshimuraMasami Murayama
    • H04L1/00H04L12/26H04L12/56H04Q11/04H04J3/14
    • H04L12/5601H04L1/0083H04L12/2697H04L43/50H04L49/1553H04L49/255H04L49/309H04Q11/0478H04J2203/0019H04L2012/5628H04L2012/5672H04L2012/5681
    • A first form of an ATM channel testing apparatus tests an ATM channel by having a test cell detector in each switch to detect whether or not the switch appropriately switches a test cell generated by a test cell generating trunk. A second form of an ATM channel testing apparatus easily tests an ATM channel by having test cell generators provided for the respective input highways sequentially generating test cells including test cell identifying information and input highway identifying information, and having test cell checkers provided respectively for the output highways simply tally the test cells by the respective input highways. A third form of an ATM channel testing apparatus tests an ATM channel with less pieces of hardware by having turnaround parts in respective ordinary trunks sequentially turn around a test cell generated by a test cell generating trunk to be finally returned to the test cell generating trunk. A fourth form of an ATM channel testing apparatus tests an ATM channel by having a test cell checker provided for each of output highways to examine whether or not the test data carried in respective octets of the payloads in extracted test cells are of consecutive values.
    • ATM信道测试装置的第一形式通过在每个交换机中具有测试小区检测器来检测ATM信道,以检测交换机是否适当地切换由测试小区产生的中继线产生的测试小区。 ATM信道测试装置的第二种形式通过为相应的输入高速公路提供测试单元发生器来容易地测试ATM信道,该测试单元发生器依次产生包括测试单元识别信息和输入公路识别信息的测试单元,并且具有分别为输出提供的测试单元检查器 高速公路通过相应的输入高速公路简单地测试单元格。 ATM信道测试装置的第三种形式通过在相应的普通中继线中具有周转部分来顺序地转换由测试小区生成中继线产生的测试小区,以最终返回到测试小区生成中继线,来测试具有较少硬件的ATM信道。 ATM信道测试装置的第四种形式通过为每个输出高速公路提供测试单元检查来检测ATM信道,以检查提取的测试小区中有效载荷的相应八位字节中承载的测试数据是否是连续值。
    • 7. 发明授权
    • Switching system for ATM dual switch system
    • ATM双交换系统的交换系统
    • US5274633A
    • 1993-12-28
    • US730808
    • 1991-07-29
    • Yumiko KatoSatoshi KakumaYasuhiro AsoYoshihiro UchidaHiroshi Miyake
    • Yumiko KatoSatoshi KakumaYasuhiro AsoYoshihiro UchidaHiroshi Miyake
    • H04L12/933H04L12/935H04L12/939H04J3/02
    • H04L49/552H04L49/15H04L49/30
    • The present invention relates to a system switching system in an exchange system in which an ATM switch for exchanging asynchronous transfer mode (ATM) cells is duplexed. In order to switch between ATM switches accurately with drop-out and overlap of cells eliminated, at the input side of the ATM switches, a bit indicating active is inserted into the header of a cell from a transmission line for application to the switch in the active system and a bit indicating standby is inserted into the header of a cell for application to the switch in the standby system and, at the output side of the ATM switches, bits in the headers of cells output from respective switches are referred to and only active indicating cells are selected to be output to a transmission line. Buffers for storing active indicating cells are provided at the outputs of the ATM switches, respectively. At the time of switching between systems, cell input to the old active system is stopped, active indicating cells are stored in the buffer in the active system, and active indicating cells stored in the buffer in the new active system are output after all the active indicating cells in the old active system have been output.
    • PCT No.PCT / JP90 / 01556 Sec。 371日期1991年7月29日 102(e)日期1991年7月29日PCT 1990年11月29日PCT PCT。 出版物WO91 / 08632 日期:1991年6月13日。本发明涉及交换系统中的系统交换系统,其中用于交换异步传输模式(ATM)小区的ATM交换机是双工的。 为了在ATM交换机之间切换准确地脱离和消除的小区的重叠,在ATM交换机的输入侧,将一个指示有效的比特从插入的传输线插入到一个小区的报头中, 活动系统和指示待机的位被插入到小区的头部中以应用于备用系统中的交换机,并且在ATM交换机的输出侧,从相应交换机输出的小区的报头中的比特被引用 活动指示单元被选择输出到传输线。 用于存储活动指示单元的缓冲器分别设置在ATM交换机的输出端。 在系统之间切换时,停止对原有活动系统的单元输入,活动指示单元存储在活动系统中的缓冲器中,并且在所有活动系统中输出存储在新的活动系统中的缓冲器中的活动指示单元 指示旧的活动系统中的单元格已经输出。