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1. 发明授权

US06930921B2 NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages 有权
公开(公告)号：US06930921B2
公开(公告)日：2005-08-16
申请号：US10989318
申请日：2004-11-17
申请人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai
发明人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C16/10 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/10
摘要： A nonvolatile semiconductor memory device includes a NAND memory cell array, booster circuit, row decoder, bit line control circuit and column decoder. In the device, the magnitude of intermediate voltage applied to the control gates of memory transistors from the booster circuit via the row decoder is changed according to the position of a selected control gate line when data is sequentially programmed into the memory transistors in the memory cell array. Alternatively, a plurality of different intermediate voltages are applied when data is simultaneously programmed into memory transistors connected to the selected control gate line.

2. 发明申请

US20050047210A1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050047210A1
公开(公告)日：2005-03-03
申请号：US10965775
申请日：2004-10-18
申请人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai , Riichiro Shirota
发明人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： A non-volatile semiconductor memory device having a write mode in which wrong writing is prevented surely. The storage device comprises a NAND cell comprising a plurality of memory transistors connected in series and also connected at one end via a select gate transistor CG1 to a bit line BL and at the other end via a select gate transistor SG2 to a common source line SL. A write voltage Vpgm is applied to a control gate of a selected memory transistor in the NAND cell and Vss is applied to the controls gates of non-select memory transistors each adjacent to the selected memory transistor to thereby write data into the select memory transistor. When a second memory transistor from the bitline BL side is selected in the writing operation, a medium voltage Vpass is applied to the control gate of a first non-selected memory transistor from the bit line BL side, and a medium voltage Vpass is applied to the control gates of third and subsequent non-selected memory transistors from the bit line BL side.
摘要翻译：具有写入模式的非易失性半导体存储器件，其中可以可靠地防止写入错误。存储装置包括NAND单元，其包括串联连接的多个存储晶体管，并且一端经选择栅极晶体管CG1连接到位线BL，另一端经由选择栅极晶体管SG2连接到公共源极线SL 。写入电压Vpgm被施加到NAND单元中所选择的存储晶体管的控制栅极，并且Vss被施加到与选择的存储晶体管相邻的非选择存储晶体管的控制栅极，从而将数据写入选择存储晶体管。当在写入操作中选择来自位线BL侧的第二存储晶体管时，从位线BL侧向第一非选择存储晶体管的控制栅极施加中等电压Vpass，并将中压Vpass施加到来自位线BL侧的第三和随后的未选择的存储器晶体管的控制栅极。

3. 发明授权

US07184309B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07184309B2
公开(公告)日：2007-02-27
申请号：US10965775
申请日：2004-10-18
申请人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai , Riichiro Shirota
发明人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10
摘要： A non-volatile semiconductor memory device having a write mode in which wrong writing is prevented surely. The storage device comprises a NAND cell comprising a plurality of memory transistors connected in series and also connected at one end via a select gate transistor CG1 to a bit line BL and at the other end via a select gate transistor SG2 to a common source line SL. A write voltage Vpgm is applied to a control gate of a selected memory transistor in the NAND cell and Vss is applied to the controls gates of non-select memory transistors each adjacent to the selected memory transistor to thereby write data into the select memory transistor. When a second memory transistor from the bitline BL side is selected in the writing operation, a medium voltage Vpass is applied to the control gate of a first non-selected memory transistor from the bit line BL side, and a medium voltage Vpass is applied to the control gates of third and subsequent non-selected memory transistors from the bit line BL side.
摘要翻译：具有写入模式的非易失性半导体存储器件，其中可以可靠地防止写入错误。存储装置包括NAND单元，其包括串联连接的多个存储晶体管，并且其一端经由选择栅极晶体管CG 1连接到位线BL，另一端经由选择栅极晶体管SG2连接到公共源极线SL。写入电压Vpgm被施加到NAND单元中所选择的存储晶体管的控制栅极，并且Vss被施加到与选择的存储晶体管相邻的非选择存储晶体管的控制栅极，从而将数据写入选择存储晶体管。当在写入操作中选择来自位线BL侧的第二存储晶体管时，从位线BL侧向第一非选择存储晶体管的控制栅极施加中等电压Vpass，并将中压Vpass施加到来自位线BL侧的第三和随后的未选择的存储器晶体管的控制栅极。

4. 发明授权

US06859395B2 NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages 有权
公开(公告)号：US06859395B2
公开(公告)日：2005-02-22
申请号：US10405233
申请日：2003-04-03
申请人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai
发明人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C16/10 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/10
摘要： A nonvolatile semiconductor memory device includes a NAND memory cell array, booster circuit, row decoder, bit line control circuit and column decoder. In the device, the magnitude of intermediate voltage applied to the control gates of memory transistors from the booster circuit via the row decoder is changed according to the position of a selected control gate line when data is sequentially programmed into the memory transistors in the memory cell array. Alternatively, a plurality of different intermediate voltages are applied when data is simultaneously programmed into memory transistors connected to the selected control gate line.

5. 发明授权

US06859394B2 NAND type non-volatile semiconductor memory device 失效
标题翻译： NAND型非易失性半导体存储器件
公开(公告)号：US06859394B2
公开(公告)日：2005-02-22
申请号：US10090995
申请日：2002-03-06
申请人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai , Riichiro Shirota
发明人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/10
摘要： A non-volatile semiconductor memory device having a write mode in which wrong writing is prevented surely. The storage device comprises a NAND cell comprising a plurality of memory transistors connected in series and also connected at one end via a select gate transistor CG1 to a bit line BL and at the other end via a select gate transistor SG2 to a common source line SL. A write voltage Vpgm is applied to a control gate of a selected memory transistor in the NAND cell and Vss is applied to the controls gates of non-select memory transistors each adjacent to the selected memory transistor to thereby write data into the select memory transistor. When a second memory transistor from the bit line BL side is selected in the writing operation, a medium voltage Vpass is applied to the control gate of a first non-selected memory transistor from the bit line BL side, and a medium voltage Vpass is applied to the control gates of third and subsequent non-selected memory transistors from the bit line BL side.
摘要翻译：具有写入模式的非易失性半导体存储器件，其中可以可靠地防止写入错误。存储装置包括NAND单元，其包括串联连接的多个存储晶体管，并且一端经选择栅极晶体管CG1连接到位线BL，另一端经由选择栅极晶体管SG2连接到公共源极线SL 。写入电压Vpgm被施加到NAND单元中所选择的存储晶体管的控制栅极，并且Vss被施加到与所选存储晶体管相邻的非选择存储晶体管的控制栅极，从而将数据写入选择存储晶体管。当在写入操作中选择来自位线BL侧的第二存储晶体管时，中间电压Vpass从位线BL侧施加到第一未选择的存储晶体管的控制栅极，施加中等电压Vpass 从位线BL侧到第三和随后的未选择的存储器晶体管的控制栅极。

6. 发明申请

US20050088890A1 NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages 有权
标题翻译： NAND型快闪EEPROM，其中通过使用不同的中间电压执行顺序编程处理
公开(公告)号：US20050088890A1
公开(公告)日：2005-04-28
申请号：US10989318
申请日：2004-11-17
申请人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai
发明人： Yasuhiko Matsunaga , Toshitake Yaegashi , Fumitaka Arai
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C16/10 , H01L27/115 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： A nonvolatile semiconductor memory device includes a NAND memory cell array, booster circuit, row decoder, bit line control circuit and column decoder. In the device, the magnitude of intermediate voltage applied to the control gates of memory transistors from the booster circuit via the row decoder is changed according to the position of a selected control gate line when data is sequentially programmed into the memory transistors in the memory cell array. Alternatively, a plurality of different intermediate voltages are applied when data is simultaneously programmed into memory transistors connected to the selected control gate line.
摘要翻译：非易失性半导体存储器件包括NAND存储单元阵列，升压电路，行解码器，位线控制电路和列解码器。在该器件中，当数据被顺序地编程到存储单元中的存储晶体管中时，根据所选择的控制栅极线的位置，改变从升压电路经由行解码器施加到存储晶体管的控制栅极的中间电压的大小数组。或者，当数据被同时编程到连接到所选择的控制栅极线的存储晶体管中时，施加多个不同的中间电压。

7. 发明授权

US06878985B2 Nonvolatile semiconductor memory device having a memory cell that includes a floating gate electrode and control gate electrode 失效
标题翻译：具有包括浮置栅电极和控制栅电极的存储单元的非易失性半导体存储器件
公开(公告)号：US06878985B2
公开(公告)日：2005-04-12
申请号：US10382772
申请日：2003-03-07
申请人： Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Akira Shimizu , Yasuhiko Matsunaga , Masayuki Ichige , Hisataka Meguro
发明人： Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Akira Shimizu , Yasuhiko Matsunaga , Masayuki Ichige , Hisataka Meguro
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： Element isolation insulating layers have an STI structure, and their upper surfaces are flat. A floating gate electrode is formed in a recess which is formed by projections of the element isolation insulating layers. The two opposing side surfaces of the floating gate electrode are covered with the element isolation insulating layers. The upper surface of the floating gate electrode is substantially leveled with the upper surfaces of the element isolation insulating layers. A gate insulating layer is formed on the floating gate electrode and element isolation insulating layers. The underlayer of this gate insulating layer is flat. A control gate electrode is formed on the gate insulating layer.
摘要翻译：元件隔离绝缘层具有STI结构，其上表面是平坦的。浮栅电极形成在由元件隔离绝缘层的突起形成的凹部中。浮置栅电极的两个相对的侧表面被元件隔离绝缘层覆盖。浮栅电极的上表面与元件隔离绝缘层的上表面基本平齐。在浮栅电极和元件隔离绝缘层上形成栅极绝缘层。该栅极绝缘层的底层是平坦的。在栅极绝缘层上形成控制栅电极。

8. 发明授权

US06816411B2 Non-volatile semiconductor storage device composed of NAND type EEPROM and deletion verification method in non-volatile semiconductor storage device 有权
标题翻译：由NAND型EEPROM构成的非易失性半导体存储装置和非易失性半导体存储装置的删除验证方法
公开(公告)号：US06816411B2
公开(公告)日：2004-11-09
申请号：US10609440
申请日：2003-07-01
申请人： Fumitaka Arai , Toshitake Yaegashi , Yasuhiko Matsunaga
发明人： Fumitaka Arai , Toshitake Yaegashi , Yasuhiko Matsunaga
IPC分类号： G11C1604
CPC分类号： G11C16/344 , G11C16/0483
摘要： A NAND column has memory cell transistors connected in series by a current passage. Word line drive circuits supply a low voltage to a word lines. A potential supply circuit supplies a high potential higher than the low potential, to a semiconductor region in which the memory cell transistors are formed, to delete contents stored in the memory cell transistors. In deletion verification which verifies that the contents stored in the memory cell transistors have been deleted, a read is executed on each of the word lines. In the read, the word line drive circuit provides the selected one of the word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.

9. 发明申请

US20080251881A1 SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM 失效
标题翻译：具有双屏障膜的半导体器件
公开(公告)号：US20080251881A1
公开(公告)日：2008-10-16
申请号：US12143597
申请日：2008-06-20
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/00
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

10. 发明授权

US07382649B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07382649B2
公开(公告)日：2008-06-03
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C11/34
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

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