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1. 发明授权

US4249145A Input-weighted charge transfer transversal filter 失效
标题翻译：输入加权电荷转移横向滤波器
公开(公告)号：US4249145A
公开(公告)日：1981-02-03
申请号：US63564
申请日：1979-08-03
申请人： Tatsuo Sakaue , Yasoji Suzuki , Tetsuya Iida
发明人： Tatsuo Sakaue , Yasoji Suzuki , Tetsuya Iida
IPC分类号： H03H15/02 , G11C27/02 , H03K17/693
CPC分类号： H03H15/023
摘要： An input-weighted charge transfer transversal filter which comprises a charge transfer device including a plurality of stages, a plurality of signal charge injectors to inject into the stages of the charge transfer device weighted signal charge packets containing an AC component and a DC component, and a sense amplifier to sense the output signal of the transversal filter from the final stage of the charge transfer device, a DC charge injector to inject a predetermined quantity of DC charge into the first stage of the charge transfer device, and charge drains respectively coupled to the stages of the charge transfer device to drain at least DC charge from stages. Due to this arrangement the quantity of DC component injected by the signal charge injectors and transferred through the charge transfer device will be reduced. This leads to an improvement in packing density and signal detecting capability of the transversal filter. According to a first embodiment of this invention, positive weighting of a signal is achieved by injecting a weighted signal charge packet into the stage of the charge transfer device, while negative weighting is achieved by draining the weighted signal charge packet from the stage. According to a second embodiment, selection between positive and negative weighting depends on the polarity of an input signal applied to the signal charge injector.
摘要翻译：一种输入加权电荷转移横向滤波器，其包括具有多级的电荷转移装置，多个信号电荷注入器，用于注入电荷转移装置的加载信号包含AC分量和DC分量的电荷分组，感测放大器，用于感测来自电荷转移装置的最后级的横向滤波器的输出信号; DC电荷注入器，用于将预定量的DC电荷注入到电荷转移装置的第一级;以及电荷引流器，分别耦合到电荷转移装置的阶段至少从阶段排出DC电荷。由于这种布置，由信号电荷注入器注入并通过电荷转移装置传送的DC分量的量将减少。这导致横向滤波器的封装密度和信号检测能力的改善。根据本发明的第一实施例，通过将加权的信号电荷分组注入到电荷转移装置的级中来实现信号的正加权，而通过从该级中排出加权的信号电荷分组来实现负加权。根据第二实施例，正和负加权之间的选择取决于施加到信号电荷注入器的输入信号的极性。

2. 发明授权

US4301427A Astable MOS FET multivibrator 失效
标题翻译：可靠的MOS FET多谐振荡器
公开(公告)号：US4301427A
公开(公告)日：1981-11-17
申请号：US129737
申请日：1980-03-12
申请人： Yasoji Suzuki , Tetsuya Iida
发明人： Yasoji Suzuki , Tetsuya Iida
IPC分类号： H03K3/354 , H03K4/501
CPC分类号： H03K3/354 , H03K4/501
摘要： A Schmitt trigger astable multivibrator circuit includes a first inverter, a second inverter whose input terminal is connected to the output terminal of the first inverter, a third inverter which is constituted by a first P-channel transistor and a first N-channel transistor serially connected and whose input and output terminals are respectively connected to the output and input terminals of the second inverter. The Schmitt trigger astable multivibrator circuit further includes a second P-channel transistor connected between a positive power supply terminal and the first P-channel transistor, and a second N-channel transistor connected between a ground terminal and the first N-channel transistor, and an input signal supplied to the first inverter is also applied to the gates of the second P-channel and N-channel transistors. The astable multivibrator also includes a time constant circuit, activated in response to the second inverter's output, which connects to the first inverter's input.
摘要翻译：施密特触发器非稳态多谐振荡器电路包括第一反相器，其输入端连接到第一反相器的输出端的第二反相器，由第一P沟道晶体管和第一N沟道晶体管串联连接的第三反相器并且其输入和输出端分别连接到第二反相器的输出端和输入端。施密特触发器非稳态多谐振荡器电路还包括连接在正电源端子和第一P沟道晶体管之间的第二P沟道晶体管，以及连接在接地端子和第一N沟道晶体管之间的第二N沟道晶体管，以及提供给第一反相器的输入信号也被施加到第二P沟道和N沟道晶体管的栅极。不稳定的多谐振荡器还包括响应于第二反相器输出而被激活的时间常数电路，其连接到第一反相器的输入端。

3. 发明授权

US4268761A Interface circuit for converting logic signal levels 失效
标题翻译：用于转换逻辑信号电平的接口电路
公开(公告)号：US4268761A
公开(公告)日：1981-05-19
申请号：US16565
申请日：1979-03-01
申请人： Yasoji Suzuki , Tetsuya Iida
发明人： Yasoji Suzuki , Tetsuya Iida
IPC分类号： H03K5/02 , H03K19/0185 , H03L5/00
CPC分类号： H03K19/018528 , H03K5/023
摘要： An input terminal of an interface circuit is connected to a first logic circuit which produces a first logic signal. The interface circuit compares the first logic signal with a reference voltage whose level is set between a high level and a low level of the first logic signal. The interface circuit converts levels of the signal compared. An output terminal of the interface circuit is connected to a second logic circuit whose signal levels are different from levels of the first logic signal and which is driven by the output signal compared and amplified.
摘要翻译：接口电路的输入端连接到产生第一逻辑信号的第一逻辑电路。接口电路将第一逻辑信号与其电平设置在第一逻辑信号的高电平和低电平之间的参考电压进行比较。接口电路转换信号的电平进行比较。接口电路的输出端子连接到第二逻辑电路，其信号电平与第一逻辑信号的电平不同，并且被比较和放大的输出信号驱动。

4. 发明授权

US4259686A Circuit for producing a polarity-reversed voltage with opposite polarity to that of a power supply voltage 失效
标题翻译：用于产生与电源电压相反的极性的极性反转电压的电路
公开(公告)号：US4259686A
公开(公告)日：1981-03-31
申请号：US947432
申请日：1978-10-02
申请人： Yasoji Suzuki , Tetsuya Iida
发明人： Yasoji Suzuki , Tetsuya Iida
IPC分类号： H02J1/00 , G05F3/24 , H02M3/07 , H03K5/003 , H03K5/00
CPC分类号： H03K5/003 , H02M3/07
摘要： An inverter is controlled by first clock pulses for converting a positive power supply into second clock pulses having a first voltage level of the power supply and a second voltage level of a reference voltage. The second clock pulses are supplied to a capacitor. The source-drain path of a first impedance varying P-FET is connected between the output terminal of the capacitor and the reference voltage and is controlled so as to take a low impedance when the second clock pulses are at the first voltage level while a high impedance when the second clock pulses are at the second voltage level. The source-drain path of a second impedance varying P-FET is connected between the output terminal and a terminal for taking out a polarity-reversed voltage. The second impedance varying P-FET is supplied at the gate with the first clock pulses so as to be controlled to take a high impendance when the second clock pulses are at the first voltage level and a low impedance when the second clock pulses are at the second level.
摘要翻译：逆变器由第一时钟脉冲控制，用于将正电源转换成具有电源的第一电压电平和参考电压的第二电压电平的第二时钟脉冲。第二个时钟脉冲被提供给电容器。第一阻抗变化P-FET的源极 - 漏极路径被连接在电容器的输出端子和参考电压之间，并且当第二时钟脉冲处于第一电压电平时被控制成低阻抗，而高当第二时钟脉冲处于第二电压电平时的阻抗。第二阻抗变化P-FET的源极 - 漏极路径连接在输出端子和用于取出极性反转电压的端子之间。第二阻抗变化P-FET在栅极处以第一时钟脉冲提供，以便当第二时钟脉冲处于第一电压电平时被控制以产生高阻抗，而当第二时钟脉冲处于第二时钟脉冲时二级

5. 发明授权

US4217535A Constant-voltage circuit with a diode and MOS transistors operating in the saturation region 失效
标题翻译：具有二极管的恒压电路和在饱和区域工作的MOS晶体管
公开(公告)号：US4217535A
公开(公告)日：1980-08-12
申请号：US864085
申请日：1977-12-23
申请人： Yasoji Suzuki , Takeshi Hitotsuyanagi , Tetsuya Iida
发明人： Yasoji Suzuki , Takeshi Hitotsuyanagi , Tetsuya Iida
IPC分类号： G01R31/36 , G05F3/24 , H02J7/10 , H03K3/26
CPC分类号： G01R19/16542 , G05F3/245 , G05F3/247
摘要： A constant-voltage circuit in which a diode and an MOS transistor are connected in series between power supply terminals between which a battery power source is connected. The MOS transistor is biased to operate in the saturation region. The forward voltage drop across the diode is kept substantially constant independent of variations in battery voltage and temperature. This constant-voltage circuit may preferably be used in a battery checker circuit for detecting the end of battery life.
摘要翻译：一种恒压电路，其中二极管和MOS晶体管串联连接在其上连接有电池电源的电源端子之间。 MOS晶体管被偏置以在饱和区域中工作。独立于电池电压和温度的变化，二极管两端的正向压降保持基本恒定。这种恒压电路可以优选地用于检测电池寿命结束的电池检查电路中。

6. 发明授权

US4267517A Operational amplifier 失效
标题翻译：运算放大器
公开(公告)号：US4267517A
公开(公告)日：1981-05-12
申请号：US965475
申请日：1978-12-01
申请人： Tetsuya Iida , Chikara Sato , Yasoji Suzuki
发明人： Tetsuya Iida , Chikara Sato , Yasoji Suzuki
IPC分类号： H03F1/30 , H03F3/30 , H03F3/45 , H03F3/16
CPC分类号： H03F1/308 , H03F3/3023 , H03F3/45183 , H03F3/45717 , H03F2203/45508 , H03F2203/45684
摘要： An operational amplifier is provided with a differential amplifier constructed by MOS transistors and a linear amplifier constructed by MOS transistors and coupled with the differential amplifier. The differential amplifier is supplied with first and second inputs. The output of the operational amplifier is derived from the output of the linear amplifier. A stabilizing circuit, which is coupled with the differential and linear amplifiers, stabilizes the output of the operational amplifier against a variation of the input DC levels to the differential amplifier.
摘要翻译：运算放大器配有由MOS晶体管构成的差分放大器和由MOS晶体管构成并与差分放大器耦合的线性放大器。差分放大器提供第一和第二输入。运算放大器的输出源自线性放大器的输出。与差分放大器和线性放大器耦合的稳定电路可以稳定运算放大器的输出，以抵抗差分放大器的输入直流电平的变化。

7. 发明授权

US06046626A Voltage transfer circuit and a booster circuit, and an IC card comprising the same 失效
标题翻译：电压传输电路和升压电路，以及包括该电路的IC卡
公开(公告)号：US06046626A
公开(公告)日：2000-04-04
申请号：US3946
申请日：1998-01-08
申请人： Yukihiro Saeki , Yasoji Suzuki
发明人： Yukihiro Saeki , Yasoji Suzuki
IPC分类号： G11C11/413 , G06K19/07 , G11C11/407 , G11C16/06 , H02M3/07 , H03K19/0948 , G05F3/02
CPC分类号： H02M3/073
摘要： A voltage transfer circuit comprises a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal, a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a clock signal, as well as a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the clock signal.
摘要翻译：电压传输电路包括第一通道类型的第一MOS晶体管，其具有连接到被提供有预定电压的第一节点的漏极端子，连接到第二节点的源极端子和栅极端子，第一MOS晶体管的第一沟道型，具有连接到第二节点的源极端子，连接到第一MOS晶体管的栅极端子的漏极端子和提供有时钟信号的栅极端子，以及具有第二沟道类型的第三MOS晶体管，其具有漏极端子连接到第二MOS晶体管的漏极端子，连接到提供有参考电压的第三节点的源极端子和被提供有时钟信号的栅极端子。

8. 发明授权

US6020869A Multi-gray level display apparatus and method of displaying an image at many gray levels 失效
公开(公告)号：US6020869A
公开(公告)日：2000-02-01
申请号：US841389
申请日：1997-04-30
申请人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
发明人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
IPC分类号： G09G3/20 , G09G3/36 , G09G3/28 , G09G3/30 , G09G5/10
CPC分类号： G09G3/3648 , G09G2310/027 , G09G3/2007 , G09G3/2018
摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

9. 发明授权

US4558234A Complementary MOSFET logic circuit 失效
标题翻译：互补MOSFET逻辑电路
公开(公告)号：US4558234A
公开(公告)日：1985-12-10
申请号：US652429
申请日：1984-09-20
申请人： Yasoji Suzuki , Kenji Matsuo
发明人： Yasoji Suzuki , Kenji Matsuo
IPC分类号： H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/092 , H03K19/003 , H03K19/01 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/01721 , H03K19/017518
摘要： Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter with a pregiven ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and pregiven threshold voltages of the FETs so as to have an input voltage characteristic adapted to an output voltage characteristic, and a buffer circuit which includes a bipolar transistor for receiving at the base thereof a signal from the output terminal of the complementary MOS inverter and an N channel MOSFET for receiving at the gate thereof an input signal applied to the complementary MOS inverter. The inverter and buffer are connected in series to one another between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof.
摘要翻译：公开了具有互补MOS反相器的互补MOSFET逻辑电路，其具有P沟道MOSFET和N沟道MOSFET的沟道宽度的预制比和FET的预定阈值电压，以便具有适于输出电压的输入电压特性特性和缓冲电路，其包括用于在其基极处接收来自互补MOS反相器的输出端的信号的双极晶体管和用于在其栅极处接收施加到互补MOS反相器的输入信号的N沟道MOSFET。反相器和缓冲器在高电位施加点和低电位施加点之间彼此串联连接，并且在其输出端产生与互补MOS反相器的逻辑输出信号相对应的信号。

10. 发明授权

US4546327A Analog signal power amplifier circuit 失效
标题翻译：模拟信号功率放大器电路
公开(公告)号：US4546327A
公开(公告)日：1985-10-08
申请号：US513308
申请日：1983-07-13
申请人： Yasoji Suzuki , Itsuo Sasaki , Shouji Abou
发明人： Yasoji Suzuki , Itsuo Sasaki , Shouji Abou
IPC分类号： H03F3/20 , H03F3/213 , H03F3/45 , H03F3/72
CPC分类号： H03F3/213 , H03F3/45183 , H03F3/72 , H03F2200/03 , H03F2200/507 , H03F2200/522 , H03F2203/45508 , H03F2203/45674
摘要： A signal corresponding to an analog input signal is supplied to one of two input terminals of a two-input, one-output MOS differential amplifier. A reference voltage signal is supplied to the other of the two input terminals of the MOS differential amplifier. A bipolar transistor having one end connected to an analog signal output terminal is driven by a signal from the output terminal of the MOS differential amplifier. A loudspeaker is driven by the bipolar transistor.
摘要翻译：对应于模拟输入信号的信号被提供给双输入一输出MOS差分放大器的两个输入端中的一个。将参考电压信号提供给MOS差分放大器的两个输入端子中的另一个。具有连接到模拟信号输出端的一端的双极晶体管由来自MOS差分放大器的输出端的信号驱动。扬声器由双极晶体管驱动。

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