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1. 发明申请

US20070260819A1 COMPLIER ASSISTED VICTIM CACHE BYPASSING 失效
标题翻译：合作协助VICTIM CACHE BYPASSING
公开(公告)号：US20070260819A1
公开(公告)日：2007-11-08
申请号：US11381563
申请日：2006-05-04
申请人： Yaoqing Gao , William Speight , Lixin Zhang
发明人： Yaoqing Gao , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/127 , Y02D10/13
摘要： A method for compiler assisted victim cache bypassing including: identifying a cache line as a candidate for victim cache bypassing; conveying a bypassing-the-victim-cache information to a hardware; and checking a state of the cache line to determine a modified state of the cache line, wherein the cache line is identified for cache bypassing if the cache line that has no reuse within a loop or loop nest and there is no immediate loop reuse or there is a substantial across loop reuse distance so that it will be replaced from both main and victim cache before being reused.
摘要翻译：一种用于编译器辅助的受害者缓存旁路的方法，包括：将高速缓存行标识为用于受害者缓存旁路的候选者; 向硬件传送绕过受害者缓存信息; 并且检查高速缓存行的状态以确定高速缓存行的修改状态，其中如果在循环或循环嵌套内没有重用的高速缓存行并且不存在立即循环重用或那里，则高速缓存行被识别用于高速缓存绕过是一个实质的跨循环重用距离，因此它将被重新使用之前被替换为主缓存和受害缓存。

2. 发明申请

US20070136535A1 System and Method for Reducing Unnecessary Cache Operations 失效
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US20070136535A1
公开(公告)日：2007-06-14
申请号：US11674960
申请日：2007-02-14
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

3. 发明申请

US20060277366A1 System and method of managing cache hierarchies with adaptive mechanisms 失效
标题翻译：用自适应机制管理缓存层次的系统和方法
公开(公告)号：US20060277366A1
公开(公告)日：2006-12-07
申请号：US11143328
申请日：2005-06-02
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/0822
摘要： A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.
摘要翻译：一种使用自适应机制管理缓存层次结构的系统和方法。本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存（源高速缓存）中选择用于逐出的数据块，检查数据结构以确定是否存在指示数据块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器，并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。此外，本发明的优选实施例包括响应于确定条目存在于数据结构中，从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块内存缓存被驱逐。

4. 发明申请

US20060155934A1 System and method for reducing unnecessary cache operations 审中-公开
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US20060155934A1
公开(公告)日：2006-07-13
申请号：US11032875
申请日：2005-01-11
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

5. 发明申请

US20070101067A1 System and method for contention-based cache performance optimization 失效
标题翻译：用于基于争用的缓存性能优化的系统和方法
公开(公告)号：US20070101067A1
公开(公告)日：2007-05-03
申请号：US11260555
申请日：2005-10-27
申请人： Hazim Shafi , William Speight
发明人： Hazim Shafi , William Speight
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0817 , G06F12/0897 , G06F2212/2542
摘要： A data processing unit, method, and computer-usable medium for contention-based cache performance optimization. Two or more processing cores are coupled by an interconnect. Coupled to the interconnect is a memory hierarchy that includes a collection of caches. Resource utilization over a time interval is detected over the interconnect. Responsive to detecting a threshold of resource utilization of the interconnect, a functional mode of a cache from the collection of caches is selectively enabled.
摘要翻译：一种用于基于争用的缓存性能优化的数据处理单元，方法和计算机可用介质。两个或多个处理核心通过互连耦合。连接到互连是包含高速缓存集合的存储器层次结构。通过互连检测在一段时间间隔内的资源利用率。响应于检测互连的资源利用的阈值，选择性地启用来自高速缓存集合的高速缓存的功能模式。

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