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1. 发明申请

US20130337327A1 CATHODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY, METHOD FOR MANUFACTURING SAME, AND LITHIUM SECONDARY BATTERY INCLUDING SAME 有权
标题翻译：用于锂二次电池的阴极活性材料，其制造方法和包括其的锂二次电池
公开(公告)号：US20130337327A1
公开(公告)日：2013-12-19
申请号：US13885939
申请日：2011-11-17
申请人： Yang-Kook Sun , Won-Gi Kim , Seung-Min Oh
发明人： Yang-Kook Sun , Won-Gi Kim , Seung-Min Oh
IPC分类号： H01M4/04 , H01M4/54 , H01M4/485 , H01M4/525 , H01M4/505
CPC分类号： H01M4/5825 , H01M4/0471 , H01M4/1397 , H01M4/366 , H01M4/485 , H01M4/505 , H01M4/525 , H01M4/54 , H01M10/052 , Y02E60/122
摘要： The present invention relates to a cathode active material for a lithium secondary battery comprising: a core including a compound represented by chemical formula 1, and a shell including a compound represented by chemical formula 2, wherein the material composition of the core and the material composition of the shell are different; and a lithium secondary battery including the cathode active material for a lithium secondary battery.
摘要翻译：锂二次电池用正极活性物质本发明涉及锂二次电池用正极活性物质，其特征在于，具有由化学式1表示的化合物的核心和包含化学式2表示的化合物的壳体，其中，芯材的组成和材料组成的壳是不同的; 以及包含锂二次电池用正极活性物质的锂二次电池。

2. 发明授权

US09728783B2 Cathode active material for lithium secondary battery, method for manufacturing same, and lithium secondary battery including same 有权
公开(公告)号：US09728783B2
公开(公告)日：2017-08-08
申请号：US13885939
申请日：2011-11-17
申请人： Yang-Kook Sun , Won-Gi Kim , Seung-Min Oh
发明人： Yang-Kook Sun , Won-Gi Kim , Seung-Min Oh
IPC分类号： H01M4/58 , H01M4/04 , H01M4/525 , H01M4/505 , H01M4/485 , H01M4/54 , H01M4/1397 , H01M4/36 , H01M10/052
CPC分类号： H01M4/5825 , H01M4/0471 , H01M4/1397 , H01M4/366 , H01M4/485 , H01M4/505 , H01M4/525 , H01M4/54 , H01M10/052 , Y02E60/122
摘要： The present invention relates to a cathode active material for a lithium secondary battery comprising: a core including a compound represented by chemical formula 1, and a shell including a compound represented by chemical formula 2, wherein the material composition of the core and the material composition of the shell are different; and a lithium secondary battery including the cathode active material for a lithium secondary battery.

3. 发明授权

US07919988B2 Output circuit and driving method thereof 失效
标题翻译：输出电路及其驱动方法
公开(公告)号：US07919988B2
公开(公告)日：2011-04-05
申请号：US12493843
申请日：2009-06-29
申请人： Seung-Min Oh
发明人： Seung-Min Oh
IPC分类号： H03K19/094 , H03K19/0185
CPC分类号： H03K19/018585 , H03K19/00361
摘要： An output circuit includes a pre-driving unit configured to drive an input signal by using a different driving power according to an output operation mode and generate pull-up and pull-down signals corresponding to the resultant input signal and an output driving unit configured to output data in response to the pull-up and pull-down signals.
摘要翻译：输出电路包括：预驱动单元，被配置为根据输出操作模式通过使用不同的驱动功率来驱动输入信号，并产生与所得到的输入信号相对应的上拉和下拉信号;以及输出驱动单元，输出数据响应于上拉和下拉信号。

4. 发明授权

US07671622B2 On-die-termination control circuit and method 失效
标题翻译：片上终端控制电路及方法
公开(公告)号：US07671622B2
公开(公告)日：2010-03-02
申请号：US12157285
申请日：2008-06-09
申请人： Seung-Min Oh , Ho-Youb Cho
发明人： Seung-Min Oh , Ho-Youb Cho
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H03K19/017
摘要： On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.
摘要翻译：片上终端控制电路包括用于检测掉电模式的模式检测单元和被配置为在断电模式下延迟开/关控制信号的掉电延迟。片上终端控制电路设置有移位寄存器，其被配置为在非掉电模式下与移位时钟同步地延迟导通/截止控制信号，并且在不断电的情况下传送接收无延迟的接通/断开控制信号，断电延迟，被配置为在掉电模式下延迟开/关控制信号，并且不在非掉电模式下延迟开/关控制信号;以及控制器，被配置为控制使能/ 根据由通过移位寄存器的通/断控制信号提供的片上终止操作的使能/禁止定时的信息以及断电延迟来禁止片上终止操作。

5. 发明申请

US20100039143A1 OUTPUT CIRCUIT AND DRIVING METHOD THEREOF 失效
标题翻译：输出电路及其驱动方法
公开(公告)号：US20100039143A1
公开(公告)日：2010-02-18
申请号：US12493843
申请日：2009-06-29
申请人： Seung-Min Oh
发明人： Seung-Min Oh
IPC分类号： H03K3/00
CPC分类号： H03K19/018585 , H03K19/00361
摘要： An output circuit includes a pre-driving unit configured to drive an input signal by using a different driving power according to an output operation mode and generate pull-up and pull-down signals corresponding to the resultant input signal and an output driving unit configured to output data in response to the pull-up and pull-down signals.
摘要翻译：输出电路包括：预驱动单元，被配置为根据输出操作模式通过使用不同的驱动功率来驱动输入信号，并产生与所得到的输入信号相对应的上拉和下拉信号;以及输出驱动单元，输出数据响应于上拉和下拉信号。

6. 发明授权

US07379376B2 Internal address generator 有权
公开(公告)号：US07379376B2
公开(公告)日：2008-05-27
申请号：US11478083
申请日：2006-06-30
申请人： Seung-Min Oh , Yong-Bok An
发明人： Seung-Min Oh , Yong-Bok An
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C11/4087
摘要： An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

7. 发明授权

US08837231B2 Integrated circuit, memory system, and operation method thereof 有权
标题翻译：集成电路，存储器系统及其操作方法
公开(公告)号：US08837231B2
公开(公告)日：2014-09-16
申请号：US13340015
申请日：2011-12-29
申请人： Seung-Min Oh
发明人： Seung-Min Oh
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/1093 , G11C7/1084 , G11C7/222
摘要： An integrated circuit includes an input pad configured to receive a low-speed signal and a high-speed signal, a high-speed buffer coupled to the input pad, a low-speed buffer coupled to the input pad, a strobe input unit configured to receive a strobe signal for indicating an input of the high-speed signal to the input pad, and a buffer control unit configured to control an activation of the high-speed buffer in response to the strobe signal.
摘要翻译：集成电路包括被配置为接收低速信号和高速信号的输入焊盘，耦合到输入焊盘的高速缓冲器，耦合到输入焊盘的低速缓冲器，选通输入单元，被配置为接收用于指示对输入焊盘的高速信号的输入的选通信号，以及配置为响应于选通信号来控制高速缓冲器的激活的缓冲器控制单元。

8. 发明授权

US08611161B2 Integrated circuit, system including the same, memory, and memory system 有权
标题翻译：集成电路，系统包括相同的内存和内存系统
公开(公告)号：US08611161B2
公开(公告)日：2013-12-17
申请号：US13334016
申请日：2011-12-21
申请人： Seung-Min Oh
发明人： Seung-Min Oh
IPC分类号： G11C7/10
CPC分类号： G11C7/1084 , G11C7/1093 , G11C7/222
摘要： A system includes integrated circuit chip including a first buffer configured to receive signals and a second buffer configured to receive signals, wherein the first buffer receives signals of a higher frequency than the second buffer, a controller chip configured to control the integrated circuit chip, an I/O channel formed between the controller chip and the integrated circuit chip to transfer a first signal and a second speed signal, wherein the first signal has a higher frequency than the second signal, and a status channel formed between the controller chip and the integrated circuit chip to transfer at least one status signal, wherein the integrated circuit chip is configured to select one of the first buffer and the second buffer and actives the selected buffer in response to the at least one status signal and receive a signal transferred through the I/O channel.
摘要翻译：一种系统包括：集成电路芯片，包括被配置为接收信号的第一缓冲器和被配置为接收信号的第二缓冲器，其中所述第一缓冲器接收比所述第二缓冲器更高频率的信号;控制器芯片，被配置为控制所述集成电路芯片， I / O通道形成在控制器芯片和集成电路芯片之间以传送第一信号和第二速度信号，其中第一信号具有比第二信号更高的频率，以及在控制器芯片和集成电路之间形成的状态通道电路芯片以传送至少一个状态信号，其中所述集成电路芯片被配置为响应于所述至少一个状态信号选择所述第一缓冲器和所述第二缓冲器中的一个并且激活所选择的缓冲器，并且接收通过所述I / O通道。

9. 发明授权

US07876635B2 Sense amplifier driving control circuit and method 失效
标题翻译：感应放大器驱动控制电路及方法
公开(公告)号：US07876635B2
公开(公告)日：2011-01-25
申请号：US12427934
申请日：2009-04-22
申请人： Seung-Min Oh
发明人： Seung-Min Oh
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1045 , G11C11/4074 , G11C11/4091
摘要： A sense amplifier driving control circuit has a stable discharge characteristic by differently controlling the discharge of a node having a driving voltage according to the change of an organization of a semiconductor memory device. The sense amplifier driving control circuit includes a pull-down driving block configured to provide a pull-down voltage for a pull-down operation of the sense amplifier, a pull-up driving block configured to sequentially provide a first voltage for the overdrive and a second voltage for the normal drive as a pull-up voltage for a pull-up operation of the sense amplifier, wherein a voltage level of the second voltage is lower than that of the first voltage, and a discharging block configured to discharge the node having the second voltage by controlling a amount of the discharging according to an organization of the semiconductor memory device.
摘要翻译：读出放大器驱动控制电路具有稳定的放电特性，通过根据半导体存储器件的组织变化来不同地控制具有驱动电压的节点的放电。读出放大器驱动控制电路包括下拉驱动块，其被配置为提供用于读出放大器的下拉操作的下拉电压，上拉驱动块被配置为顺序地提供用于过驱动的第一电压和用于正常驱动的第二电压作为用于读出放大器的上拉操作的上拉电压，其中第二电压的电压电平低于第一电压的电压电平，以及放电块，其被配置为对具有通过根据半导体存储器件的组织控制放电量来控制第二电压。

10. 发明申请

US20070070742A1 Test mode controller 失效
标题翻译：测试模式控制器
公开(公告)号：US20070070742A1
公开(公告)日：2007-03-29
申请号：US11529274
申请日：2006-09-29
申请人： Seung-Min Oh
发明人： Seung-Min Oh
IPC分类号： G11C29/00
CPC分类号： G11C29/46 , G11C29/006 , G11C29/14
摘要： A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable test and a wafer burn-in test to generate a reset signal and a control signal generating block for receiving a plurality of input signals activated in a wafer burn-in test to generate a plurality of test control signals in response to the reset signal and a programmable test signal activated in a programmable stress test.
摘要翻译：测试模式控制器能够通过整合构成两个测试电路的锁存单元来减少芯片面积和不必要的电流消耗。测试模式控制器包括用于确定可编程测试和晶片老化测试之间的测试模式以产生复位信号的测试控制块，以及用于接收在晶片老化中激活的多个输入信号的控制信号生成模块测试以响应于复位信号和在可编程压力测试中激活的可编程测试信号来产生多个测试控制信号。

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