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1. 发明申请

US20080192552A1 Internal address generator 审中-公开
标题翻译：内部地址发生器
公开(公告)号：US20080192552A1
公开(公告)日：2008-08-14
申请号：US12081317
申请日：2008-04-15
申请人： Seung-Min Oh , Yong-Bok An
发明人： Seung-Min Oh , Yong-Bok An
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/18 , G11C11/4087
摘要： An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.
摘要翻译：内部地址发生器包括多个列地址发生器，模式列地址发生器和驱动时钟发生器。响应于读取驱动时钟，每个列产生器接收对应的地址，附加延迟和CAS延迟以产生内部读取地址，并响应于写入驱动时钟生成内部写入地址。模式列地址生成器接收对应的地址，加法等待时间和CAS等待时间，以响应于带宽读驱动时钟生成模式读地址，并响应于带宽写驱动时钟生成模式写地址。驱动时钟发生器接收附加延迟信号，带宽信号，写使能信号和时钟以产生读驱动时钟，写驱动时钟，带宽读驱动时钟和带宽写驱动时钟。

2. 发明申请

US20070070781A1 Internal address generator 有权
标题翻译：内部地址发生器
公开(公告)号：US20070070781A1
公开(公告)日：2007-03-29
申请号：US11478083
申请日：2006-06-30
申请人： Seung-Min Oh , Yong-Bok An
发明人： Seung-Min Oh , Yong-Bok An
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C11/4087
摘要： An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.
摘要翻译：内部地址发生器包括多个列地址发生器，模式列地址发生器和驱动时钟发生器。响应于读取驱动时钟，每个列产生器接收对应的地址，附加延迟和CAS延迟以产生内部读取地址，并响应于写入驱动时钟生成内部写入地址。模式列地址生成器接收对应的地址，加法等待时间和CAS等待时间，以响应于带宽读驱动时钟生成模式读地址，并响应于带宽写驱动时钟生成模式写地址。驱动时钟发生器接收附加延迟信号，带宽信号，写使能信号和时钟以产生读驱动时钟，写驱动时钟，带宽读驱动时钟和带宽写驱动时钟。

3. 发明授权

US07379376B2 Internal address generator 有权
公开(公告)号：US07379376B2
公开(公告)日：2008-05-27
申请号：US11478083
申请日：2006-06-30
申请人： Seung-Min Oh , Yong-Bok An
发明人： Seung-Min Oh , Yong-Bok An
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C11/4087
摘要： An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

4. 发明授权

US07522467B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07522467B2
公开(公告)日：2009-04-21
申请号：US11526830
申请日：2006-09-26
申请人： Yong-Bok An
发明人： Yong-Bok An
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C8/12 , G11C7/1045 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/109 , G11C7/22 , G11C11/4076 , G11C11/4087 , G11C11/4093 , G11C29/26
摘要： A semiconductor memory device analyzes tRCD inferiority by simultaneously interlock-controlling an enable time of column address and an access time of cell data. The semiconductor memory device includes a bank column address controller for decoding an bank address and a bank control signal to provide a bank column address, and an enable controller for outputting a plurality of control signals with different states in response to a test mode signal, outputting the bank control signal of which enable delay time is controlled by a selective activation state of the plurality of control signals in a read/write operation mode, and controlling a column address enable signal to activate the bank column address to have the same enable delay time as the bank control signal.
摘要翻译：半导体存储器件通过同时互锁地控制列地址的使能时间和单元数据的访问时间来分析tRCD劣势。半导体存储器件包括用于解码存储体地址的存储体列地址控制器和用于提供存储体列地址的存储体控制信号，以及使能控制器，用于响应于测试模式信号输出具有不同状态的多个控制信号，输出在读/写操作模式下，通过多个控制信号的选择性激活状态控制其使能延迟时间的存储体控制信号，并且控制列地址使能信号以激活存储体列地址以具有相同的使能延迟时间作为银行控制信号。

5. 发明申请

US20080143420A1 Internal voltage trimming circuit for use in a semiconductor memory device and method thereof 有权
标题翻译：用于半导体存储器件的内部电压调整电路及其方法
公开(公告)号：US20080143420A1
公开(公告)日：2008-06-19
申请号：US12071426
申请日：2008-02-21
申请人： Yong-Bok An
发明人： Yong-Bok An
IPC分类号： G06G7/28
CPC分类号： G11C5/147
摘要： An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.
摘要翻译：内部电源调整电路及其方法在半导体存储器件中单独地或同时地对多个电源电压进行电平调整。内部电源调整电路包括：修整控制信号发生器，用于通过使用输入的地址信号产生修整选择信号和修整使能信号;以及内部电源电压控制器，用于通过使用修整来控制内部电源电压的电平选择信号，其在修整使能信号的控制下输出。

6. 发明申请

US20070002643A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070002643A1
公开(公告)日：2007-01-04
申请号：US11313961
申请日：2005-12-22
申请人： Yong-Bok An
发明人： Yong-Bok An
IPC分类号： G11C7/00
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/22
摘要： A semiconductor memory device for broadening a data I/O window includes: a buffer driving block for generating a buffer driving signal in response to an additive delay signal and a CAS delay signal, wherein an activation period of the buffer driving signal is determined based on the additive delay signal and a combination of delayed additive delay signals; and a data buffer for receiving an external data at an activation of the buffer driving signal.
摘要翻译：一种用于加宽数据I / O窗口的半导体存储器件包括：缓冲器驱动块，用于响应于加法延迟信号和CAS延迟信号产生缓冲器驱动信号，其中缓冲器驱动信号的激活周期基于加法延迟信号和延迟加法延迟信号的组合; 以及用于在激活缓冲器驱动信号时接收外部数据的数据缓冲器。

7. 发明申请

US20100290266A1 COMMAND PROCESSING CIRCUIT AND PHASE CHANGE MEMORY DEVICE USING THE SAME 失效
标题翻译：指令处理电路和使用相同的相变存储器件
公开(公告)号：US20100290266A1
公开(公告)日：2010-11-18
申请号：US12489690
申请日：2009-06-23
申请人： Yong-Bok An
发明人： Yong-Bok An
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/22 , G11C13/0004
摘要： A command processing circuit for generating internal command signals corresponding to a plurality of unit internal command signals sequentially applied during a plurality of command cycles, the command processing circuit includes a first command latching unit configured to latch a first unit internal command signal applied in a first command cycle and a second command latching unit configured to latch a second unit internal command signal in response to the first unit internal command signal latched in the first command latching unit in a second command cycle after the first command cycle, and output an internal command signal corresponding to the first unit internal command signal and the second unit internal command signal.
摘要翻译：一种命令处理电路，用于产生对应于在多个命令周期期间顺序施加的多个单位内部命令信号的内部命令信号，所述命令处理电路包括：第一命令锁存单元，用于锁存第一个命令信号，命令循环和第二命令锁存单元，被配置为在第一命令循环之后的第二命令循环中响应于在第一命令锁存单元中锁存的第一单元内部命令信号来锁存第二单元内部命令信号，并且输出内部命令信号对应于第一单元内部命令信号和第二单元内部命令信号。

8. 发明授权

US07312627B2 Decoding circuit for on die termination in semiconductor memory device and its method 有权
标题翻译：半导体存储器件中芯片端接解码电路及其方法
公开(公告)号：US07312627B2
公开(公告)日：2007-12-25
申请号：US11017645
申请日：2004-12-22
申请人： Yong-Bok An
发明人： Yong-Bok An
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C8/10 , G11C11/4096 , G11C2207/105
摘要： A decoding circuit of an on die termination (ODT) control signal for stably performing an ODT operation. The decoding circuit includes: a latch unit for receiving a plurality of input signals and for holding previous output signals of the latch unit when the plurality of input signals are in predetermined logic levels; and a decoding unit for decoding output signals of the latch unit in order to control ODT operation.
摘要翻译：一种用于稳定地执行ODT操作的管芯端接（ODT）控制信号的解码电路。解码电路包括：锁存单元，用于在多个输入信号处于预定逻辑电平时接收多个输入信号并用于保持锁存单元的先前输出信号; 以及解码单元，用于解码锁存单元的输出信号，以便控制ODT操作。

9. 发明申请

US20070147148A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070147148A1
公开(公告)日：2007-06-28
申请号：US11526830
申请日：2006-09-26
申请人： Yong-Bok An
发明人： Yong-Bok An
IPC分类号： G11C8/00 , G11C29/00 , G11C7/00
CPC分类号： G11C8/12 , G11C7/1045 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/109 , G11C7/22 , G11C11/4076 , G11C11/4087 , G11C11/4093 , G11C29/26
摘要： A semiconductor memory device analyzes tRCD inferiority by simultaneously interlock-controlling an enable time of column address and an access time of cell data. The semiconductor memory device includes a bank column address controller for decoding an bank address and a bank control signal to provide a bank column address, and an enable controller for outputting a plurality of control signals with different states in response to a test mode signal, outputting the bank control signal of which enable delay time is controlled by a selective activation state of the plurality of control signals in a read/write operation mode, and controlling a column address enable signal to activate the bank column address to have the same enable delay time as the bank control signal.
摘要翻译：半导体存储器件通过同时互锁地控制列地址的使能时间和单元数据的访问时间来分析tRCD劣势。半导体存储器件包括用于解码存储体地址的存储体列地址控制器和用于提供存储体列地址的存储体控制信号，以及使能控制器，用于响应于测试模式信号输出具有不同状态的多个控制信号，输出在读/写操作模式下，通过多个控制信号的选择性激活状态控制其使能延迟时间的存储体控制信号，并且控制列地址使能信号以激活存储体列地址以具有相同的使能延迟时间作为银行控制信号。

10. 发明申请

US20060002225A1 Semiconductor memory device capable of stably setting mode register set and method therefor 有权
公开(公告)号：US20060002225A1
公开(公告)日：2006-01-05
申请号：US11030485
申请日：2005-01-05
申请人： Yong-Bok An
发明人： Yong-Bok An
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1045
摘要： A semiconductor memory device having a mode register set (MRS) includes: a decoding unit for decoding a plurality of address signals included in the MRS and outputting a plurality of decoded signals; and an output unit for outputting a plurality of configuration signals and activating one of the plurality of configuration signals in response to the plurality of decoded signals, wherein the output unit keeps its previous output signals if more than one of the plurality of decoded signals are activated.

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