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1. 发明申请

US20090153186A1 On-die-termination control circuit and method 有权
标题翻译：片上终端控制电路及方法
公开(公告)号：US20090153186A1
公开(公告)日：2009-06-18
申请号：US12157298
申请日：2008-06-09
申请人： Seung-Min Oh , Ho-Youb Cho
发明人： Seung-Min Oh , Ho-Youb Cho
IPC分类号： H03K19/003
CPC分类号： H04L25/0292
摘要： On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off timing of an ODT operation.
摘要翻译：片上终端控制电路包括：时钟发生器，被配置为响应于开/关控制信号产生移位时钟; 以及移位寄存器，被配置为与所述移位时钟同步地延迟所述接通/断开控制信号，以控制ODT操作的开/关定时。

2. 发明授权

US07626417B2 On-die-termination control circuit and method 有权
公开(公告)号：US07626417B2
公开(公告)日：2009-12-01
申请号：US12157298
申请日：2008-06-09
申请人： Seung-Min Oh , Ho-Youb Cho
发明人： Seung-Min Oh , Ho-Youb Cho
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0292
摘要： On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off timing of an ODT operation.

3. 发明申请

US20090153185A1 On-die-termination control circuit and method 失效
标题翻译：片上终端控制电路及方法
公开(公告)号：US20090153185A1
公开(公告)日：2009-06-18
申请号：US12157285
申请日：2008-06-09
申请人： Seung-Min Oh , Ho-Youb Cho
发明人： Seung-Min Oh , Ho-Youb Cho
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/017
摘要： On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.
摘要翻译：片上终端控制电路包括用于检测掉电模式的模式检测单元和被配置为在断电模式下延迟开/关控制信号的掉电延迟。片上终端控制电路设置有移位寄存器，其被配置为在非掉电模式下与移位时钟同步地延迟导通/截止控制信号，并且在不断电的情况下传送接收无延迟的接通/断开控制信号，断电延迟，被配置为在掉电模式下延迟开/关控制信号，并且不在非掉电模式下延迟开/关控制信号;以及控制器，被配置为控制使能/ 根据由通过移位寄存器的通/断控制信号提供的片上终止操作的使能/禁止定时的信息以及断电延迟来禁止片上终止操作。

4. 发明授权

US07671622B2 On-die-termination control circuit and method 失效
标题翻译：片上终端控制电路及方法
公开(公告)号：US07671622B2
公开(公告)日：2010-03-02
申请号：US12157285
申请日：2008-06-09
申请人： Seung-Min Oh , Ho-Youb Cho
发明人： Seung-Min Oh , Ho-Youb Cho
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H03K19/017
摘要： On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.
摘要翻译：片上终端控制电路包括用于检测掉电模式的模式检测单元和被配置为在断电模式下延迟开/关控制信号的掉电延迟。片上终端控制电路设置有移位寄存器，其被配置为在非掉电模式下与移位时钟同步地延迟导通/截止控制信号，并且在不断电的情况下传送接收无延迟的接通/断开控制信号，断电延迟，被配置为在掉电模式下延迟开/关控制信号，并且不在非掉电模式下延迟开/关控制信号;以及控制器，被配置为控制使能/ 根据由通过移位寄存器的通/断控制信号提供的片上终止操作的使能/禁止定时的信息以及断电延迟来禁止片上终止操作。

5. 发明授权

US08009504B2 Semiconductor memory input/output device 有权
标题翻译：半导体存储器输入/输出装置
公开(公告)号：US08009504B2
公开(公告)日：2011-08-30
申请号：US12339389
申请日：2008-12-19
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C7/22
摘要： A semiconductor memory input/output device includes selection pads used to input and output signals for multiple operation modes and having multiple functions, a control signal generator for outputting setting signals and a mask control signal, a lower input/output unit including a lower output buffer for outputting a read data strobe signal to a selection pad and a lower input buffer for receiving a lower data mask signal from the selection pad, and selecting one operation of the lower output buffer and the lower input buffer, and an upper input/output unit including an upper output buffer for outputting an inverted read data strobe signal to the second selection pad and an upper input buffer for receiving an upper data mask signal from the second selection pad, and selecting one operation of the upper output buffer and the upper input buffer.
摘要翻译：半导体存储器输入/输出装置包括用于输入和输出用于多个操作模式的信号并具有多个功能的选择焊盘，用于输出设置信号的控制信号发生器和掩模控制信号，包括下部输出缓冲器用于将选择焊盘的读取数据选通信号输出到选择焊盘的下部数据屏蔽信号，以及选择下部输出缓冲器和下部输入缓冲器的一个动作，以及上部输入输出部包括用于向第二选择焊盘输出反转的读数据选通信号的上输出缓冲器和用于从第二选择焊盘接收上数据掩码信号的上输入缓冲器，以及选择上输出缓冲器和上输入缓冲器的一个操作。

6. 发明授权

US07697348B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07697348B2
公开(公告)日：2010-04-13
申请号：US12366357
申请日：2009-02-05
申请人： Ho-Youb Cho
发明人： Ho-Youb Cho
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1045 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C2207/107
摘要： A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector.
摘要翻译：第一输入缓冲器接收顺序输入的第一数据。第一数据选择器根据数据输入模式选择性地传送来自第一输入缓冲器的第一数据。第一数据对准电路对准并输出来自第一数据选择器的数据。第二输入缓冲器根据数据输入模式接收顺序输入的第二数据。第二数据选择器根据数据输入模式选择性地传送第一输入缓冲器或第二输入缓冲器的数据。第一数据对准电路对准并输出来自第二数据选择器的数据。

7. 发明授权

US07573757B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07573757B2
公开(公告)日：2009-08-11
申请号：US12073294
申请日：2008-03-04
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C11/063
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： Disclosed herein is a semiconductor memory device for reducing a current consumption used for operating a write command or a read command. The semiconductor memory device includes a global data latch unit for latching a global data loaded on a global data line in response to a first write enable signal to thereby generate a global latch data; a local data write driving unit for receiving the global latch data to output a local data to a local data line in response to a second write enable signal; and a write driver control unit for generating the first write enable signal and the second write enable signal to inactivate the first write enable signal when a write operation is not performed.
摘要翻译：这里公开了一种用于减少用于操作写入命令或读取命令的电流消耗的半导体存储器件。半导体存储器件包括全局数据锁存单元，用于响应于第一写使能信号来锁存加载在全局数据线上的全局数据，从而生成全局锁存数据; 本地数据写驱动单元，用于接收全局锁存数据，以响应于第二写使能信号将本地数据输出到本地数据线; 以及写入驱动器控制单元，用于在不执行写入操作时产生第一写入使能信号和第二写入使能信号以使第一写入使能信号失活。

8. 发明授权

US07359256B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07359256B2
公开(公告)日：2008-04-15
申请号：US11312610
申请日：2005-12-21
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： Disclosed herein is a semiconductor memory device for reducing a current consumption used for operating a write command or a read command. The semiconductor memory device includes a global data latch unit for latching a global data loaded on a global data line in response to a first write enable signal to thereby generate a global latch data; a local data write driving unit for receiving the global latch data to output a local data to a local data line in response to a second write enable signal; and a write driver control unit for generating the first write enable signal and the second write enable signal to inactivate the first write enable signal when a write operation is not performed.
摘要翻译：这里公开了一种用于减少用于操作写入命令或读取命令的电流消耗的半导体存储器件。半导体存储器件包括全局数据锁存单元，用于响应于第一写使能信号来锁存加载在全局数据线上的全局数据，从而生成全局锁存数据; 本地数据写驱动单元，用于接收全局锁存数据，以响应于第二写使能信号将本地数据输出到本地数据线; 以及写入驱动器控制单元，用于在不执行写入操作时产生第一写入使能信号和第二写入使能信号以使第一写入使能信号失活。

9. 发明申请

US20070070676A1 Pipe latch device of semiconductor memory device 有权
标题翻译：半导体存储器件的锁闩装置
公开(公告)号：US20070070676A1
公开(公告)日：2007-03-29
申请号：US11477384
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.
摘要翻译：管闩锁装置包括：输出控制器，用于基于DLL时钟信号和驱动信号输出第一和第二输出控制信号组; 用于产生输入控制信号组的输入控制器; 以及管锁存单元，用于当相应的输入控制信号被激活时将数据锁存在数据线上，并且当相应的输出控制信号被激活时输出锁存的数据，其中输出控制器包括多个移位器，每个移位器用于延迟输入数据信号通过半时钟和一个时钟与DLL时钟信号和驱动信号同步地输出第一和第二输出信号; 以及多个输出控制信号驱动器，用于基于第一和第二输出信号输出第一和第二输出控制信号组。

10. 发明申请

US20050162945A1 Semiconductor memory device having repair circuit 失效
标题翻译：具有修复电路的半导体存储器件
公开(公告)号：US20050162945A1
公开(公告)日：2005-07-28
申请号：US11015419
申请日：2004-12-20
申请人： Sang-Hee Kang , Sung-Joo Ha , Ho-Youb Cho
发明人： Sang-Hee Kang , Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/808
摘要： A semiconductor memory device, including: a plurality of banks each of which includes a plurality of memory cells, a plurality of redundancy memory cells for replacing a defective memory cell and a repair circuit, having a plurality of fuse sets, for substituting an address to thereby access the redundancy memory cell instead of the defective memory cell; and a common repair circuit, having a plurality of fuse sets, for substituting the address in order to replace the defective memory cell with the redundancy memory cell included in any of the plurality of banks.
摘要翻译：一种半导体存储器件，包括：多个存储体，每个存储体包括多个存储单元，用于替换有缺陷存储单元的多个冗余存储单元和具有多个熔丝组的修复电路，用于将地址替换为从而访问冗余存储单元而不是有缺陷的存储单元; 以及具有多个熔丝组的通用修复电路，用于代替所述地址以便用所述多个存储体中的任一个中包含的所述冗余存储单元替换所述有缺陷的存储单元。

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