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1. 发明申请

US20220109048A1 High Voltage Gallium Nitride Field Effect Transistor 有权
公开(公告)号：US20220109048A1
公开(公告)日：2022-04-07
申请号：US17487117
申请日：2021-09-28
申请人： Zhanming Li , Yan-Fei Liu , Wai Tung Ng
发明人： Zhanming Li , Yan-Fei Liu , Wai Tung Ng
IPC分类号： H01L29/06 , H01L29/20 , H01L29/778 , H01L29/66
摘要： A gallium nitride (GaN) semiconductor device has first and second electrodes connected to a top metal layer disposed in complementary first and second irregular shapes, each irregular shape including a wide connection area at a first end, a tapered area, and a narrow area at a second end. The first and second irregular shapes are arranged adjacent each other along complementary edges such that a gap between the complementary edges is of substantially constant width. The first and second wide connection areas include pads for wire bond or land grid array electrical connections to external circuitry. The first and second irregular shapes for source and drain metal of a field effect transistor (FET) or high electron mobility transistor (HEMT) allows the width of the gate finger to be short so that electrical current injected from the gate can reach all portions of the gate fingers efficiently during high frequency switching, making the topology suitable for high voltage power devices.

2. 发明授权

US11107755B2 Packaging for lateral high voltage GaN power devices 有权
公开(公告)号：US11107755B2
公开(公告)日：2021-08-31
申请号：US16871026
申请日：2020-05-10
申请人： Zhanming Li , Yue Fu , Yan-Fei Liu
发明人： Zhanming Li , Yue Fu , Yan-Fei Liu
IPC分类号： H01L23/495 , H01L23/00
摘要： Packaging methods and structures for lateral high voltage gallium nitride (GaN) devices achieve electrical isolation while also maintaining thermal dissipation. The electrical isolation reduces or eliminates vertical leakage current, improving high voltage performance. The packages may use or be compatible standards such as JEDEC, which reduces packaging cost and facilitates implementation of the packaged devices in conventional circuit design approaches.

3. 发明申请

US20190379374A1 High-Side Gate Driver for Gallium Nitride Integrated Circuits 审中-公开
公开(公告)号：US20190379374A1
公开(公告)日：2019-12-12
申请号：US16423138
申请日：2019-05-27
申请人： Zhanming Li , Yan-Fei Liu , Yue Fu , Wai Tung Ng
发明人： Zhanming Li , Yan-Fei Liu , Yue Fu , Wai Tung Ng
IPC分类号： H03K17/30 , H03K17/06 , H03K17/22
摘要： A gate driver circuit for a gallium nitride (GaN) power transistor includes a RS-flipflop that receives a first pulse train at an S input terminal and a second pulse train at an R input terminal, and produces an output pulse train, and an amplifier that amplifies the output pulse train and produces a gate driver signal for the GaN power transistor. The RS-flipflop and the amplifier may be implemented together on a GaN monolithic integrated circuit, optionally together with the GaN power transistor. The GaN power transistor may be a high-side switch of a half-bridge circuit. The RS-flipflop may be implemented with enhancement mode and depletion mode GaN high electron mobility transistors (HEMTs). Embodiments avoid drawbacks of prior hybrid (e.g., silicon-GaN) approaches, such as parasitic inductances from bonding wires and on-board metal traces, especially at high operating frequencies, as well as reduce implementation cost and improve performance.

4. 发明申请

US20180309383A1 Five-Level Inverter Topology with High Voltage Utilization Ratio 审中-公开
公开(公告)号：US20180309383A1
公开(公告)日：2018-10-25
申请号：US15767721
申请日：2016-11-07
申请人： Yan-Fei LIU
发明人： Hongliang Wang , Yan-Fei Liu
IPC分类号： H02M7/483 , H02M1/32 , H02M7/5387
CPC分类号： H02M7/483 , H02M1/32 , H02M7/487 , H02M7/5387 , Y02E10/56
摘要： A five-voltage level inverter topology circuit, and three-phase and five-voltage level inverter topology circuit, suitable for use with two serial-connected direct current (DC) power sources (C1, C2), comprise: a half-bridge inverter circuit comprising a first circuit module (M1) and a second circuit module (M2). The half-bridge inverter circuit can output 5 voltage levels including a 0V level. The five-voltage level inverter topology circuit adopts a 5-voltage level half-bridge structure, and only requires an alternating current (AC) filtering inductor (L1), thereby reducing a system cost and size, removing a leakage current, and providing high efficiency.

5. 发明授权

US07612602B2 Resonant gate drive circuits 有权
标题翻译：谐振栅极驱动电路
公开(公告)号：US07612602B2
公开(公告)日：2009-11-03
申请号：US11045055
申请日：2005-01-31
申请人： Zhihua Yang , Yan-Fei Liu
发明人： Zhihua Yang , Yan-Fei Liu
IPC分类号： H03K17/74
CPC分类号： H03K17/04163 , H02M1/08 , H03K17/04123
摘要： A resonate gate drive circuit for driving at least one power switching devices recovers energy loss for charging and discharging the input capacitance of the power switching devices. The gate drive circuit charging and discharging the gate capacitor with a high level current, so the switching loss of the power switching devices can also be reduced. The gate drive circuit can clamp and keep the voltage across the gate capacitor to a certain level while the power switching devices turn on, and it can also clamp and keep the voltage across the gate capacitor to almost zero while the power switching devices turn off. The gate drive circuit comprises four small semiconductor bidirectional conducting switching devices connected in full-bridge configuration. An inductor is connected to the two junctions of the full-bridge configuration to help switching the current direction. A capacitor in series with the inductor is necessary for some applications. A bootstrap circuit, which is widely used in conventional gate drive circuitry, is also necessary for this resonant gate drive circuit when it is adopted for high-side and low-side applications.
摘要翻译：用于驱动至少一个电力开关装置的谐振栅极驱动电路恢复用于对功率开关装置的输入电容进行充电和放电的能量损失。栅极驱动电路以高电平电流对栅极电容器进行充电和放电，因此也可以降低功率开关器件的开关损耗。栅极驱动电路可以在功率开关器件导通的同时将栅极电容器两端的电压钳位并保持一定水平，并且在电源开关器件关闭时，它也可以钳位并保持栅极电容器两端的电压几乎为零。栅极驱动电路包括以全桥配置连接的四个小型半导体双向导通开关装置。电感器连接到全桥配置的两个连接点，以帮助切换电流方向。与电感器串联的电容器对于某些应用是必需的。当用于高边和低边应用时，该谐振栅极驱动电路也需要用于常规栅极驱动电路的自举电路。

6. 发明申请

US20080122422A1 Parallel Current Mode Control Using a Direct Duty Cycle Algorithm with Low Computational Requirements to Perform Power Factor Correction 失效
标题翻译：使用具有低计算要求的直接占空比算法进行功率因数校正的并联电流模式控制
公开(公告)号：US20080122422A1
公开(公告)日：2008-05-29
申请号：US11951228
申请日：2007-12-05
申请人： Wanfeng Zhang , Yan-Fei Liu , Bin Wu
发明人： Wanfeng Zhang , Yan-Fei Liu , Bin Wu
IPC分类号： H02M3/156
CPC分类号： H02M3/157 , H02M1/4225 , H02M2001/4275 , Y02B70/126 , Y02P80/112
摘要： A method and apparatus to implement parallel current mode control that is suitable for digital and analog implementation. A duty cycle algorithm is composed of a voltage term and a parallel current term which depends on the inductor current change between the inductor current value at the beginning of a switching cycle and the reference inductor current value at the end of that switching cycle. Parallel current mode control can be applied to all DC-DC converters, including both non-isolated and isolated topologies. It can also be applied to AC-DC converters with power factor correction.
摘要翻译：一种适用于数字和模拟实现的并行电流模式控制的方法和装置。占空比算法由电压项和并联电流项组成，取决于开关周期开始时的电感电流值与开关周期结束时的参考电感电流值之间的电感电流变化。并联电流模式控制可应用于所有DC-DC转换器，包括非隔离和隔离拓扑。它也可以应用于具有功率因数校正的AC-DC转换器。

7. 发明授权

US06980783B2 Apparatus and method of controlling low frequency load currents drawn from a DC source in a telecommunications system 有权
标题翻译：控制从电信系统中的直流源抽取的低频负载电流的装置和方法
公开(公告)号：US06980783B2
公开(公告)日：2005-12-27
申请号：US10265168
申请日：2002-10-03
申请人： Yan-Fei Liu , Raymond Orr , Kai Xu
发明人： Yan-Fei Liu , Raymond Orr , Kai Xu
IPC分类号： H02M3/156 , H04B1/10
CPC分类号： H02M3/156 , H02M2001/0009 , H02M2001/0022
摘要： A circuit controls the low frequency load currents drawn by components of telecommunications systems. The circuit includes a power converter, a first sense circuit, a second sense circuit, a comparator, and a power converter control circuit. The power converter control circuit controls the power converter's duty cycle in accordance with the input signal compared to a reference. In this manner, the low frequency load currents may be easily and economically controlled.
摘要翻译：电路控制电信系统组件所绘制的低频负载电流。该电路包括功率转换器，第一感测电路，第二感测电路，比较器和功率转换器控制电路。功率转换器控制电路根据与参考相比的输入信号来控制功率转换器的占空比。以这种方式，可以容易且经济地控制低频负载电流。

8. 发明申请

US20050024894A1 Isolated DC-DC converters 有权
标题翻译：隔离式DC-DC转换器
公开(公告)号：US20050024894A1
公开(公告)日：2005-02-03
申请号：US10729970
申请日：2003-12-09
申请人： Yan-Fei Liu , Sheng Ye
发明人： Yan-Fei Liu , Sheng Ye
IPC分类号： H02M3/28 , H02M3/335 , H02J1/00
CPC分类号： H02M3/285 , H02M3/33576
摘要： One DC-DC converter includes primary side circuit between high and low side inputs including first primary winding of first transformer, and auxiliary section; and rectifier circuits, with separate secondary windings of first transformer, and in parallel with one another and output and capacitor; an output capacitor between outputs and across rectifier circuit. Auxiliary causes transfer of power from first primary to first secondary winding and operation without saturation. Another converter includes primary side circuit including primary winding of plurality of transformers, and an auxiliary section; a rectifier circuit having secondary winding of the plurality of transformers, the rectifier circuit in parallel with output and capacitor; an output capacitor between outputs and across rectifier circuit. Auxiliary section includes switches for connecting and disconnecting primary windings from input, and for resetting transformers. Alternatively, auxiliary section includes switches and capacitors. Switches and capacitors in auxiliary section shared between transformers.
摘要翻译：一个DC-DC转换器包括高低侧输入之间的初级侧电路，包括第一变压器的第一初级绕组和辅助部分; 和整流电路，具有第一变压器的单独的次级绕组，并且彼此并联并输出和电容器; 输出和整流电路之间的输出电容。辅助电源从第一次初级到次级绕组转换，无饱和操作。另一转换器包括：初级侧电路，包括多个变压器的初级绕组和辅助部分; 整流电路具有多个变压器的次级绕组，整流电路与输出和电容并联; 输出和整流电路之间的输出电容。辅助部分包括用于从输入端连接和断开初级绕组以及用于复位变压器的开关。或者，辅助部分包括开关和电容器。变压器共用的辅助部分中的开关和电容器。

9. 发明授权

US11043899B2 Zero inductor voltage converter topology with improved switch utilization 有权
公开(公告)号：US11043899B2
公开(公告)日：2021-06-22
申请号：US16576995
申请日：2019-09-20
申请人： Samuel Dylan Webb , Yan-Fei Liu
发明人： Samuel Dylan Webb , Yan-Fei Liu
IPC分类号： H02M3/07 , H02M3/158 , H02M1/08 , H02M1/00
摘要： A multi-stage, multi-level DC-DC step-down converter includes a first stage and a second stage having two identical cells connected in parallel. The first stage includes an input capacitor, four switches, and one flying capacitor. The two cells of the second stage each include four switches and one flying capacitor, and an output filter. The cells of the second stage are driven at half the switching frequency of the input stage, and provides a step-down ratio of 4:1. A third stage having four cells may be added to achieve a step-down ratio of 8:1, a fourth stage having eight cells may be added to achieve a step-down ration of 16:1, etc., each additional stage including a doubling of the number of cells connected in parallel, with all cells being substantially identical, and each stage operating at a further reduced fraction of the switching frequency. Embodiments are particularly suitable for applications such as a 48V intermediate bus architecture for servers and datacenters.

10. 发明授权

US10939553B2 Vertical-side solder method and package for power GaN devices 有权
公开(公告)号：US10939553B2
公开(公告)日：2021-03-02
申请号：US16254296
申请日：2019-01-22
申请人： Zhanming Li , Yan-Fei Liu , Yue Fu , Wai Tung Ng
发明人： Zhanming Li , Yan-Fei Liu , Yue Fu , Wai Tung Ng
IPC分类号： H01L27/18 , H05K1/18 , H01L23/31 , H01L23/34 , H01L29/20 , H01L29/778 , H05K1/02 , H05K1/11
摘要： A packaged GaN semiconductor device with improved heat dissipation is provided. A GaN device is packaged on a printed circuit board (PCB) with a vertical side of the device, and optionally the back side of the device, in thermal contact with the PCB. The packaging is compatible with surface mount technologies such as land grid array (LGA), ball grid array (BGA), and other formats. Thermal contact between the PCB and a vertical side of the device, and optionally the back side of the device, is made through solder. The solder used for the thermal contact may also connect a source terminal of the device, which also improves electrical stability of the device. The packaging is particularly suitable for GaN HEMT devices.

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