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    • 1. 发明授权
    • Touchpad with a double-layer printed circuit board structure
    • 触摸板采用双层印刷电路板结构
    • US08411065B2
    • 2013-04-02
    • US12630782
    • 2009-12-03
    • Jianbo YangBangjun HeYun YangWei Feng
    • Jianbo YangBangjun HeYun YangWei Feng
    • G06F3/042
    • G06F3/045G06F3/03547
    • The present invention provides a touchpad with a double-layer printed circuit board structure. The touchpad comprises an upper layer, a bottom layer, a first conductor; and a second conductor; wherein the upper layer is configured to act as a touch-sensitive zone, and comprises a plurality of first conductive units, a first conductive wire and a plurality of second conductive units; the bottom layer comprises a wire connecting zone and a component zone, wherein the wire connecting zone further includes a second conductive wire and a connecting line configured to be electrically coupled to the component zone; and the first conductor and the second conductor are configured to connect the upper layer to the bottom layer; wherein the first and the second conductive units are each serially-connected to form a first touch-sensitive line and a second touch-sensitive line, respectively.
    • 本发明提供一种具有双层印刷电路板结构的触摸板。 触摸板包括上层,底层,第一导体; 和第二导体; 其中所述上层被配置为用作触敏区,并且包括多个第一导电单元,第一导线和多个第二导电单元; 底层包括电线连接区域和组件区域,其中电线连接区域还包括第二导线和被配置为电耦合到组件区域的连接线; 并且所述第一导体和所述第二导体被配置为将所述上层连接到所述底层; 其中第一和第二导电单元分别串联连接以形成第一触敏线和第二触敏线。
    • 2. 发明授权
    • EEPROM cell
    • EEPROM单元
    • US08383476B2
    • 2013-02-26
    • US12888437
    • 2010-09-23
    • Sung Mun JungKian Hong LimJianbo YangSwee Tuck WooSanford Chu
    • Sung Mun JungKian Hong LimJianbo YangSwee Tuck WooSanford Chu
    • H01L21/8238
    • H01L29/7881G11C16/0433H01L21/28273H01L27/11521H01L27/11524H01L29/66825
    • A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.
    • 公开了一种形成装置的方法。 该方法包括提供准备有单元区域的基板,并在单元区域中形成第一和第二晶体管的第一和第二栅极。 第一栅极包括围绕第一子栅极的第二子栅极。 第一栅极的第一和第二子栅极由第一栅极介电层分开。 第二栅极包括围绕第一子栅极的第二子栅极。 第二栅极的第一和第二子栅极由第二栅极间介电层分开。 该方法还包括形成第一和第二晶体管的第一和第二结。 第一栅极端子形成并耦合到第一晶体管的第二子栅极。 第二栅极端子形成并耦合到至少第二晶体管的第一子栅极。
    • 3. 发明授权
    • EEPROM cell
    • EEPROM单元
    • US08383475B2
    • 2013-02-26
    • US12888431
    • 2010-09-23
    • Sung Mun JungKian Hong LimJianbo YangSwee Tuck WooSanford Chu
    • Sung Mun JungKian Hong LimJianbo YangSwee Tuck WooSanford Chu
    • H01L21/8238
    • H01L21/28273H01L27/11521H01L27/11524H01L29/66825H01L29/7881
    • A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.
    • 公开了一种形成装置的方法。 该方法包括提供制备有由其它活性区域隔离的细胞区域的基底。 在单元区域中形成第一和第二晶体管的第一和第二栅极。 第一栅极包括由第一隔间栅极介电层隔开的第一和第二子栅极。 第二栅极包括围绕第一子栅极的第二子栅极。 第二栅极的第一和第二子栅极由第二栅极间介电层分开。 形成第一和第二晶体管的第一和第二结。 该方法还包括形成耦合到第一晶体管的第二子栅极的第一栅极端子和耦合到第二晶体管的至少第一子栅极的第二栅极端子。
    • 5. 发明申请
    • EEPROM CELL
    • EEPROM单元
    • US20120074482A1
    • 2012-03-29
    • US12888431
    • 2010-09-23
    • Sung Mun JUNGKian Hong LIMJianbo YANGSwee Tuck WOOSanford CHU
    • Sung Mun JUNGKian Hong LIMJianbo YANGSwee Tuck WOOSanford CHU
    • H01L29/788H01L21/336
    • H01L21/28273H01L27/11521H01L27/11524H01L29/66825H01L29/7881
    • A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.
    • 公开了一种形成装置的方法。 该方法包括提供制备有由其它活性区域隔离的细胞区域的基底。 在单元区域中形成第一和第二晶体管的第一和第二栅极。 第一栅极包括由第一隔间栅极介电层隔开的第一和第二子栅极。 第二栅极包括围绕第一子栅极的第二子栅极。 第二栅极的第一和第二子栅极由第二栅极间介电层分开。 形成第一和第二晶体管的第一和第二结。 该方法还包括形成耦合到第一晶体管的第二子栅极的第一栅极端子和耦合到第二晶体管的至少第一子栅极的第二栅极端子。
    • 6. 发明申请
    • EEPROM CELL
    • EEPROM单元
    • US20120074483A1
    • 2012-03-29
    • US12888437
    • 2010-09-23
    • Sung Mun JUNGKian Hong LIMJianbo YANGSwee Tuck WOOSanford CHU
    • Sung Mun JUNGKian Hong LIMJianbo YANGSwee Tuck WOOSanford CHU
    • H01L29/788H01L21/336
    • H01L29/7881G11C16/0433H01L21/28273H01L27/11521H01L27/11524H01L29/66825
    • A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.
    • 公开了一种形成装置的方法。 该方法包括提供准备有单元区域的基板,并在单元区域中形成第一和第二晶体管的第一和第二栅极。 第一栅极包括围绕第一子栅极的第二子栅极。 第一栅极的第一和第二子栅极由第一栅极介电层分开。 第二栅极包括围绕第一子栅极的第二子栅极。 第二栅极的第一和第二子栅极由第二栅极间介电层分开。 该方法还包括形成第一和第二晶体管的第一和第二结。 第一栅极端子形成并耦合到第一晶体管的第二子栅极。 第二栅极端子形成并耦合到至少第二晶体管的第一子栅极。
    • 7. 发明申请
    • Touchpad with a Double-Layer Printed Circuit Board Structure
    • 具有双层印刷电路板结构的触摸板
    • US20110025615A1
    • 2011-02-03
    • US12630782
    • 2009-12-03
    • Jianbo YangBangjun HeYun YangWei Feng
    • Jianbo YangBangjun HeYun YangWei Feng
    • G06F3/041
    • G06F3/045G06F3/03547
    • The present invention provides a touchpad with a double-layer printed circuit board structure. The touchpad comprises an upper layer, a bottom layer, a first conductor; and a second conductor; wherein the upper layer is configured to act as a touch-sensitive zone, and comprises a plurality of first conductive units, a first conductive wire and a plurality of second conductive units; the bottom layer comprises a wire connecting zone and a component zone, wherein the wire connecting zone further includes a second conductive wire and a connecting line configured to be electrically coupled to the component zone; and the first conductor and the second conductor are configured to connect the upper layer to the bottom layer; wherein the first and the second conductive units are each serially-connected to form a first touch-sensitive line and a second touch-sensitive line, respectively.
    • 本发明提供一种具有双层印刷电路板结构的触摸板。 触摸板包括上层,底层,第一导体; 和第二导体; 其中所述上层被配置为用作触敏区,并且包括多个第一导电单元,第一导线和多个第二导电单元; 底层包括电线连接区域和组件区域,其中电线连接区域还包括第二导线和被配置为电耦合到组件区域的连接线; 并且所述第一导体和所述第二导体被配置为将所述上层连接到所述底层; 其中第一和第二导电单元分别串联连接以形成第一触敏线和第二触敏线。