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1. 发明授权

US08237197B2 Asymmetric channel MOSFET 失效
标题翻译：非对称沟道MOSFET
公开(公告)号：US08237197B2
公开(公告)日：2012-08-07
申请号：US12831310
申请日：2010-07-07
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.
摘要翻译：场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

2. 发明申请

US20120190160A1 ASYMMETRIC CHANNEL MOSFET 失效
公开(公告)号：US20120190160A1
公开(公告)日：2012-07-26
申请号：US13428061
申请日：2012-03-23
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L21/335
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

3. 发明申请

US20120007145A1 ASYMMETRIC CHANNEL MOSFET 失效
标题翻译：不对称通道MOSFET
公开(公告)号：US20120007145A1
公开(公告)日：2012-01-12
申请号：US12831310
申请日：2010-07-07
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L29/165 , H01L21/336 , H01L21/8234 , H01L27/088
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.
摘要翻译：场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

4. 发明授权

US08298897B2 Asymmetric channel MOSFET 失效
公开(公告)号：US08298897B2
公开(公告)日：2012-10-30
申请号：US13428061
申请日：2012-03-23
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

5. 发明申请

US20080153217A1 DUAL LAYER STRESS LINER FOR MOSFETS 失效
标题翻译：用于MOSFET的双层应力衬垫
公开(公告)号：US20080153217A1
公开(公告)日：2008-06-26
申请号：US11616147
申请日：2006-12-26
申请人： Deleep R. Nair , Christopher V. Baiocco , Xiangdong Chen , Junjung Kim , Jae-eun Park , Daewon Yang
发明人： Deleep R. Nair , Christopher V. Baiocco , Xiangdong Chen , Junjung Kim , Jae-eun Park , Daewon Yang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7843 , H01L21/31604 , H01L29/66575
摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.
摘要翻译：制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。栅极结构和导体区域构成晶体管。为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。第二功率电平比第一功率电平高（例如，至少高5倍）。

6. 发明授权

US07521308B2 Dual layer stress liner for MOSFETS 失效
标题翻译：用于MOSFET的双层应力衬垫
公开(公告)号：US07521308B2
公开(公告)日：2009-04-21
申请号：US11616147
申请日：2006-12-26
申请人： Deleep R. Nair , Christopher V. Baiocco , Xiangdong Chen , Junjung Kim , Jae-eun Park , Daewon Yang
发明人： Deleep R. Nair , Christopher V. Baiocco , Xiangdong Chen , Junjung Kim , Jae-eun Park , Daewon Yang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/31604 , H01L29/66575
摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.
摘要翻译：制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。栅极结构和导体区域构成晶体管。为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。第二功率电平比第一功率电平高（例如，至少高5倍）。

7. 发明授权

US07612414B2 Overlapped stressed liners for improved contacts 失效
标题翻译：重叠的应力衬垫改善了接触
公开(公告)号：US07612414B2
公开(公告)日：2009-11-03
申请号：US11693254
申请日：2007-03-29
申请人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
发明人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
IPC分类号： H01L21/8238 , H01L23/18
CPC分类号： H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
摘要翻译：提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

8. 发明申请

US20080237737A1 OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS 失效
标题翻译：用于改进联系人的超重压力衬管
公开(公告)号：US20080237737A1
公开(公告)日：2008-10-02
申请号：US11693254
申请日：2007-03-29
申请人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
发明人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
摘要翻译：提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

9. 发明授权

US08120058B2 High-drive current MOSFET 有权
标题翻译：高驱动电流MOSFET
公开(公告)号：US08120058B2
公开(公告)日：2012-02-21
申请号：US12607116
申请日：2009-10-28
申请人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
发明人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
IPC分类号： H01L29/739
CPC分类号： H01L29/7394 , H01L29/66325
摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
摘要翻译：一种形成具有不对称源极和漏极的半导体器件的方法。在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。还提供了通过上述方法形成的半导体器件。

10. 发明申请

US20110095333A1 HIGH-DRIVE CURRENT MOSFET 有权
标题翻译：高驱动电流MOSFET
公开(公告)号：US20110095333A1
公开(公告)日：2011-04-28
申请号：US12607116
申请日：2009-10-28
申请人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
发明人： Jae-Eun Park , Xinlin Wang , Xiangdong Chen
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7394 , H01L29/66325
摘要： A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.
摘要翻译：一种形成具有不对称源极和漏极的半导体器件的方法。在一个实施例中，该方法包括在具有第一导电性阱的衬底的第一部分上形成栅极结构。第二导电性的第二导电性和漏极区的源极区域形成在第一导电性的阱内，在与存在栅极结构的基板的第一部分相邻的基板的一部分中。在漏极区域内形成第二导电性的掺杂区域，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性的阱提供，基极由漏极区域的第二导电性和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。还提供了通过上述方法形成的半导体器件。

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