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1. 发明授权

US08916472B2 Interconnect formation using a sidewall mask layer 有权
标题翻译：使用侧壁掩模层的互连形成
公开(公告)号：US08916472B2
公开(公告)日：2014-12-23
申请号：US13562426
申请日：2012-07-31
申请人： Xiang Hu , Mingmei Wang , Liu Huang
发明人： Xiang Hu , Mingmei Wang , Liu Huang
IPC分类号： H01L21/308 , H01L21/768 , H01L21/033
CPC分类号： H01L21/76811 , H01L21/0337 , H01L21/31144
摘要： Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch.
摘要翻译：本文描述的实施例提供了使用侧壁掩模层的半导体器件中的互连形成方法。具体而言，在去除了先前在硬掩模上形成的平坦化层之后，在半导体器件的合并通孔区域中的硬掩模上沉积侧壁掩模层。侧壁掩模层被共形沉积在硬掩模上，并且像在牺牲层中一样起作用以在随后的通孔蚀刻期间保护硬掩模。这在通孔蚀刻期间减小了通孔临界尺寸（CD）并且沿着硬掩模线方向降低了CD伸长率。

2. 发明申请

US20140038412A1 INTERCONNECT FORMATION USING A SIDEWALL MASK LAYER 有权
标题翻译：使用扇形遮蔽层互连形成
公开(公告)号：US20140038412A1
公开(公告)日：2014-02-06
申请号：US13562426
申请日：2012-07-31
申请人： Xiang Hu , Mingmei Wang , Liu Huang
发明人： Xiang Hu , Mingmei Wang , Liu Huang
IPC分类号： H01L21/308
CPC分类号： H01L21/76811 , H01L21/0337 , H01L21/31144
摘要： Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch.
摘要翻译：本文描述的实施例提供了使用侧壁掩模层的半导体器件中的互连形成方法。具体而言，在去除了先前在硬掩模上形成的平坦化层之后，在半导体器件的合并通孔区域中的硬掩模上沉积侧壁掩模层。侧壁掩模层被共形沉积在硬掩模上，并且像在牺牲层中一样起作用以在随后的通孔蚀刻期间保护硬掩模。这在通孔蚀刻期间减小了通孔临界尺寸（CD）并且沿着硬掩模线方向降低了CD伸长率。

3. 发明授权

US07052932B2 Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication 有权
标题翻译：用于双重镶嵌制造中Cu阻挡层和蚀刻停止层的氧掺杂SiC
公开(公告)号：US07052932B2
公开(公告)日：2006-05-30
申请号：US10785520
申请日：2004-02-24
申请人： Liu Huang , John Sudijono , Koh Yee Wee
发明人： Liu Huang , John Sudijono , Koh Yee Wee
IPC分类号： H01L21/00
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method of forming a dual damascene structure with improved performance is described. A first etch stop layer comprised of oxygen doped SiC is deposited on a SiC barrier layer to form a composite barrier/etch stop layer on a substrate. The remainder of the damascene stack is formed by sequentially depositing a first dielectric layer, a second oxygen doped SiC etch stop layer, and a second dielectric layer. A via and overlying trench are formed and filled with a diffusion barrier layer and a metal layer. The oxygen doped SiC layers have a lower dielectric constant than SiC or SIGN and a higher breakdown field than SiC. The etch selectivity of a C4F8/Ar etch for a SiCOH layer relative to the oxygen doped SiC layer is at least 6:1 because of a lower oxygen content in the oxygen doped SiC layer.
摘要翻译：描述了一种形成具有改进性能的双镶嵌结构的方法。由氧掺杂的SiC构成的第一蚀刻停止层沉积在SiC阻挡层上，以在衬底上形成复合势垒/蚀刻停止层。镶嵌层的剩余部分通过依次沉积第一介电层，第二氧掺杂的SiC蚀刻停止层和第二介电层而形成。形成通孔和上覆沟槽并填充有扩散阻挡层和金属层。氧掺杂的SiC层具有比SiC或SIGN更低的介电常数和比SiC更高的击穿场。对于SiCOH层，相对于氧掺杂的SiC层，C 4 Si 8 N / Ar蚀刻的蚀刻选择性至少为6:1，因为氧含量低氧掺杂的SiC层。

4. 发明授权

US09006102B2 Hybrid TSV and method for forming the same 有权
标题翻译：混合TSV及其形成方法
公开(公告)号：US09006102B2
公开(公告)日：2015-04-14
申请号：US13091277
申请日：2011-04-21
申请人： Yu Hong , Liu Huang , Zhao Feng
发明人： Yu Hong , Liu Huang , Zhao Feng
IPC分类号： H01L21/40 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76847 , H01L21/76877 , H01L21/76898 , H01L23/528 , H01L23/53238 , H01L23/53257 , H01L2924/00013 , H01L2924/0002 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.
摘要翻译：通常，本文公开的主题涉及导电通孔元件，例如穿硅通孔（TSV's）及其形成方法。形成本文公开的导电通孔元件的一个说明性方法包括在衬底中形成通孔，通孔延伸穿过形成在衬底上方的层间电介质层，以及形成在层间介质层下方并延伸到衬底中的器件层。该方法还包括形成导电通孔元件的第一部分，该第一部分包括在通孔开口的底部部分中的第一导电接触材料，以及形成导电通孔元件的第二部分，该导电通孔元件包括不同于第一导电接触件的第二导电接触材料在通孔开口的上部和第一部分上方的材料。

5. 发明授权

US08354327B2 Scheme for planarizing through-silicon vias 有权
标题翻译：平面化硅通孔的方案
公开(公告)号：US08354327B2
公开(公告)日：2013-01-15
申请号：US13091473
申请日：2011-04-21
申请人： Chen Zengxiang , Zhao Feng , Liu Huang , Yuan Shaoning
发明人： Chen Zengxiang , Zhao Feng , Liu Huang , Yuan Shaoning
IPC分类号： H01L21/76
CPC分类号： H01L21/3212 , H01L21/7684 , H01L21/76898
摘要： Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.
摘要翻译：通常，本文公开的主题涉及导电通孔元件，例如穿硅通孔（TSV's）及其形成方法。本文公开的一种说明性方法包括在半导体器件中形成的通孔开口上方形成隔离材料层，该通孔开口延伸到半导体器件的衬底中。该方法还包括执行第一平坦化处理以去除形成在通孔开口外部的隔离材料层的至少上部，并且在执行第一平面化处理之后在通孔开口内形成导电通孔元件。

6. 发明授权

US06872633B2 Deposition and sputter etch approach to extend the gap fill capability of HDP CVD process to ≦0.10 microns 有权
标题翻译：沉积和溅射蚀刻方法将HDP CVD工艺的间隙填充能力扩展到<= 0.10微米
公开(公告)号：US06872633B2
公开(公告)日：2005-03-29
申请号：US10161014
申请日：2002-05-31
申请人： Liu Huang , John Sudijono
发明人： Liu Huang , John Sudijono
IPC分类号： H01L21/762 , H01L21/31
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A method of filling an STI feature with a dielectric material using a HDP CVD technique is described. By omitting an inert carrier gas like argon in the first CVD step, a small keyhole in a SiO2 layer is formed near the top of the trench. A sputter etch step in the same CVD chamber then removes dielectric material above the keyhole. A second CVD step completely fills the STI trench which is free of voids and forms a layer above the adjacent nitride layer. The nitride layer serves as an etch stop during a CMP step to lower the level of dielectric material until it is coplanar with the nitride layer. The method is low cost since all deposition and sputter etch steps are performed in an existing CVD tool and the same tool is useful in forming trenches of various sizes ranging from below 0.13 micron to above 0.25 micron.
摘要翻译：描述了使用HDP CVD技术用电介质材料填充STI特征的方法。通过在第一CVD步骤中省略诸如氩的惰性载气，在沟槽的顶部附近形成SiO 2层中的小键孔。然后在相同的CVD室中的溅射蚀刻步骤除去键孔上方的介电材料。第二CVD步骤完全填充没有空隙的STI沟槽，并在相邻的氮化物层上方形成一层。在CMP步骤期间，氮化物层用作蚀刻停止层，以降低电介质材料的水平，直到其与氮化物层共面。该方法是低成本的，因为在现有的CVD工具中进行所有沉积和溅射蚀刻步骤，并且相同的工具可用于形成从0.13微米至0.25微米以下的各种尺寸的沟槽。

7. 发明申请

US20120270391A1 SCHEME FOR PLANARIZING THROUGH-SILICON VIAS 有权
标题翻译：用于平面穿透硅石的方案
公开(公告)号：US20120270391A1
公开(公告)日：2012-10-25
申请号：US13091473
申请日：2011-04-21
申请人： Chen Zengxiang , Zhao Feng , Liu Huang , Yuan Shaoning
发明人： Chen Zengxiang , Zhao Feng , Liu Huang , Yuan Shaoning
IPC分类号： H01L21/768
CPC分类号： H01L21/3212 , H01L21/7684 , H01L21/76898
摘要： Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.
摘要翻译：通常，本文公开的主题涉及导电通孔元件，例如穿硅通孔（TSV's）及其形成方法。本文公开的一种说明性方法包括在半导体器件中形成的通孔开口上方形成隔离材料层，该通孔开口延伸到半导体器件的衬底中。该方法还包括执行第一平坦化处理以去除形成在通孔开口外部的隔离材料层的至少上部，并且在执行第一平面化处理之后在通孔开口内形成导电通孔元件。

8. 发明授权

US07186640B2 Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics 有权
标题翻译：含有低介电常数电介质的铜镶嵌互连的富硅氧化物
公开(公告)号：US07186640B2
公开(公告)日：2007-03-06
申请号：US10177855
申请日：2002-06-20
申请人： Liu Huang , John Sudijono , Simon Chooi
发明人： Liu Huang , John Sudijono , Simon Chooi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76829 , H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/76807 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating at least one damascene opening comprising the following steps. A structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower low-k dielectric layer is formed over the dielectric barrier layer. An upper low-k dielectric layer is formed over the lower low-k dielectric layer. An SRO etch stop layer is formed between the lower low-k dielectric layer and the upper low-k dielectric layer and/or an SRO hard mask layer is formed over the upper low-k dielectric layer. At least the upper and lower low-k dielectric layers are patterned to form the at least one damascene opening exposing at least a portion of the at least one conductive structure, wherein the at least one SRO layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.
摘要翻译：一种制造至少一个镶嵌开口的方法，包括以下步骤。提供具有至少一个暴露的导电结构的结构。在所述结构和所述至少一个暴露的导电结构上的介电阻挡层。在介电阻挡层上方形成较低的低k电介质层。在较低的低k电介质层上形成上部低k电介质层。在下部低k电介质层和上部低k电介质层之间形成SRO蚀刻停止层和/或在上部低k电介质层上形成SRO硬掩模层。至少上下低k电介质层被图案化以形成暴露至少一部分至少一个导电结构的至少一个镶嵌开口，其中至少一个SRO层相对于较低的和上部低k电介质层。

9. 发明授权

US07148157B2 Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslon 有权
标题翻译：使用phoslon（PNO）进行无边界接触制造，用于双镶嵌制造的蚀刻停止/阻挡层和形成光芒的方法
公开(公告)号：US07148157B2
公开(公告)日：2006-12-12
申请号：US10278133
申请日：2002-10-22
申请人： Hsia Liang Choo , John Sudijono , Liu Huang , Tan Juan Boon
发明人： Hsia Liang Choo , John Sudijono , Liu Huang , Tan Juan Boon
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02112 , C23C16/308 , H01L21/02274 , H01L21/3145 , H01L21/76801 , H01L21/76807 , H01L21/76829
摘要： A method of forming phoslon (PNO) comprising the following steps. A CVD reaction chamber having a reaction temperature of from about 300 to 600° C. is provided. From about 10 to 200 sccm PH3 gas, from about 50 to 4000 sccm N2 gas and from about 50 to 1000 sccm NH3 gas are introduced into the CVD reaction chamber. Either from about 10 to 200 sccm O2 gas or from about 50 to 1000 sccm N2O gas is introduced into the CVD reaction chamber. An HFRF power of from about 0 watts to 4 kilowatts is also employed. An LFRF power of from about 0 to 5000 watts may also be employed. Employing a phoslon etch stop layer in a borderless contact fabrication. Employing a phoslon lower etch stop layer and/or a phoslon middle etch stop layer in a dual damascene fabrication.
摘要翻译：一种形成太阳能（PNO）的方法，包括以下步骤。提供反应温度为约300-600℃的CVD反应室。约10至200sccm的PH 3气体，约50至4000sccm的N 2气体和约50至1000sccm的NH 3气体被引入到CVD反应室中。将约10至200sccm的O 2气体或约50至1000sccm的N 2 O气体引入CVD反应室中。还使用约0瓦至4千瓦的HFRF功率。还可以使用约0至5000瓦特的LFRF功率。在无边界接触制造中采用光锡蚀刻停止层。在双镶嵌制造中使用磷光下蚀刻停止层和/或磷光中间蚀刻停止层。

10. 发明申请

US20120267788A1 Hybrid TSV and Method for Forming the Same 有权
标题翻译：混合TSV及其形成方法
公开(公告)号：US20120267788A1
公开(公告)日：2012-10-25
申请号：US13091277
申请日：2011-04-21
申请人： Yu Hong , Liu Huang , Zhao Feng
发明人： Yu Hong , Liu Huang , Zhao Feng
IPC分类号： H01L21/283 , H01L23/48
CPC分类号： H01L23/481 , H01L21/76847 , H01L21/76877 , H01L21/76898 , H01L23/528 , H01L23/53238 , H01L23/53257 , H01L2924/00013 , H01L2924/0002 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.
摘要翻译：通常，本文公开的主题涉及导电通孔元件，例如穿硅通孔（TSV's）及其形成方法。形成本文公开的导电通孔元件的一个说明性方法包括在衬底中形成通孔，通孔延伸穿过形成在衬底上方的层间电介质层，以及形成在层间介质层下方并延伸到衬底中的器件层。该方法还包括形成导电通孔元件的第一部分，该第一部分包括在通孔开口的底部部分中的第一导电接触材料，以及形成导电通孔元件的第二部分，该导电通孔元件包括不同于第一导电接触件的第二导电接触材料在通孔开口的上部和第一部分上方的材料。

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