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1. 发明授权

US06566197B2 Method for fabricating connection structure between segment transistor and memory cell region of flash memory device 有权
公开(公告)号：US06566197B2
公开(公告)日：2003-05-20
申请号：US09939765
申请日：2001-08-28
申请人： Wook-Hyun Kwon , Kee-Yeol Na , Sang-Bum Lee , Yong-Hee Kim , Woong-Lim Choi
发明人： Wook-Hyun Kwon , Kee-Yeol Na , Sang-Bum Lee , Yong-Hee Kim , Woong-Lim Choi
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L23/485 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a flash memory device, electrical connections between segment transistors and memory cells are accurately achieved by forming the segment transistors before forming the memory cells. When forming the segment transistors, a first impurity is implanted into a substrate to form a first source and a first drain. A second impurity is then implanted into the substrate to form a conductive line to be used as a common bit line for the memory cells, and simultaneously form a second source below the first source and a second drain below the first drain of the segment transistor. As such, the common bit lines of the memory cells and the second sources of the segment transistors are formed to be electrically connected together with more reliability.

2. 发明授权

US08354708B2 Methods of forming and operating semiconductor device 有权
标题翻译：半导体器件的形成和操作方法
公开(公告)号：US08354708B2
公开(公告)日：2013-01-15
申请号：US13087643
申请日：2011-04-15
申请人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
发明人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.
摘要翻译：提供半导体器件以及形成和操作半导体器件的方法。半导体器件可以包括从半导体衬底延伸并且二维地设置在半导体衬底上的有源柱，在一个方向上连接有源柱的上部互连，与上部互连交叉的下部互连，并且设置在有源柱之间，跨越上部的字线互连并且布置在活动柱之间，以及布置在字线和活动柱之间的数据存储图案。

3. 发明申请

US20070268749A1 Method for operating non-volatile memory device 审中-公开
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20070268749A1
公开(公告)日：2007-11-22
申请号：US11802282
申请日：2007-05-22
申请人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
发明人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0483 , G11C16/3409 , G11C16/345
摘要： A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.
摘要翻译：公开了一种操作非易失性存储器件的方法。存储单元包括分离源极区和漏极区的沟道区，隧道绝缘层，电荷存储层和形成在沟道区上的栅电极。该方法包括向栅电极施加负电压并向源区和漏区中的至少一个施加正电压，以将空穴注入到隧道绝缘层中，从而去除俘获在隧道绝缘层中的电子。

4. 发明申请

US20060099756A1 Methods of forming non-volatile memory device having floating gate 失效
标题翻译：形成具有浮动栅极的非易失性存储器件的方法
公开(公告)号：US20060099756A1
公开(公告)日：2006-05-11
申请号：US11268038
申请日：2005-11-07
申请人： Wook-Hyun Kwon
发明人： Wook-Hyun Kwon
IPC分类号： H01L21/8238
CPC分类号： H01L27/11546 , H01L21/82345 , H01L27/105 , H01L27/11526 , H01L29/66825
摘要： Embodiments of the present invention are directed to methods for forming non-volatile memory devices. A substrate is provided that has a cell region, a first peripheral region, and second peripheral region. A tunnel insulating layer is formed on the substrate in the cell region. A preliminary floating gate is formed on the tunnel insulating layer in the cell region. A blocking insulating layer is formed on the substrate in the cell region, the first peripheral region, and the second peripheral region. A conductive layer is formed on the blocking insulating layer in the cell region, the first peripheral region, and the second peripheral region. The conductive layer and the blocking insulating layer in the first and second peripheral regions are removed to expose at least a portion of the substrate in the first and second peripheral regions. First and second gate insulating layers are respectively formed on the exposed substrate of the first and second peripheral regions. An undoped silicon layer is formed on the substrate in the cell region, the first peripheral region, and the second peripheral region. The undoped silicon layer in the first peripheral region is doped with impurities of a first-conductivity-type. The undoped silicon layer in the second peripheral region is doped with impurities of a second-conductivity-type.
摘要翻译：本发明的实施例涉及用于形成非易失性存储器件的方法。提供了具有单元区域，第一周边区域和第二外围区域的基板。在单元区域的基板上形成隧道绝缘层。在电池区域的隧道绝缘层上形成初步浮栅。在单元区域，第一周边区域和第二周边区域中的基板上形成阻挡绝缘层。在单元区域，第一周边区域和第二周边区域中的阻挡绝缘层上形成导电层。去除第一和第二周边区域中的导电层和阻挡绝缘层，以暴露第一和第二周边区域中的至少一部分基板。第一和第二栅极绝缘层分别形成在第一和第二周边区域的暴露的基板上。在单元区域，第一周边区域和第二周边区域的基板上形成未掺杂的硅层。第一周边区域中未掺杂的硅层掺杂有第一导电类型的杂质。第二周边区域中未掺杂的硅层掺杂有第二导电类型的杂质。

5. 发明授权

US07547943B2 Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same 失效
标题翻译：包括具有凹陷通道的选择晶体管的非易失性存储器件及其制造方法
公开(公告)号：US07547943B2
公开(公告)日：2009-06-16
申请号：US11022181
申请日：2004-12-22
申请人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
发明人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
IPC分类号： H01L29/94
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/66621 , H01L29/66825 , H01L29/7834 , H01L29/7881
摘要： A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.
摘要翻译： NAND型非易失性存储器件包括衬底和设置在衬底上以限定有源区的器件隔离层。第一和第二选择晶体管设置在有源区域中，使得第一和第二选择晶体管中的每一个具有凹陷通道。多个存储晶体管设置在第一选择晶体管和第二选择晶体管之间的有源区中。

6. 发明申请

US20070105309A1 Contactless nonvolatile memory device and method of forming the same 有权
公开(公告)号：US20070105309A1
公开(公告)日：2007-05-10
申请号：US11590620
申请日：2006-10-31
申请人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
发明人： Wook-Hyun Kwon , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing the mask patterns, floating gates between the word lines and the recess regions, and an intergate dielectric pattern between the floating gates and the word lines, and to expose the recess regions and the mask patterns between word lines.

7. 发明申请

US20060023558A1 Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same 失效
公开(公告)号：US20060023558A1
公开(公告)日：2006-02-02
申请号：US11022181
申请日：2004-12-22
申请人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
发明人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
IPC分类号： G11C8/00
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/66621 , H01L29/66825 , H01L29/7834 , H01L29/7881
摘要： A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.

8. 发明申请

US20080094923A1 Non-volatile memory device capable of reducing threshold voltage distribution 有权
标题翻译：能够降低阈值电压分布的非易失性存储器件
公开(公告)号：US20080094923A1
公开(公告)日：2008-04-24
申请号：US11636205
申请日：2006-12-09
申请人： Wook-Hyun Kwon
发明人： Wook-Hyun Kwon
IPC分类号： G11C7/00
CPC分类号： G11C16/3454 , G11C29/70
摘要： A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It is determined whether each of the programmed memory cells has been successfully programmed based on the results of the reading step. The programming of memory cells that have been determined to have been successfully programmed are inhibited. The programming, reading, determining and inhibiting steps are repeated until each of the selected memory cells has been determined to have been successfully programmed. A memory cell that has been previously determined to have been successfully programmed and inhibited is uninhibited and subsequently re-programmed when it is determined that the previously inhibited memory cell is no longer successfully programmed.
摘要翻译：一种用于编程闪存设备的方法，其包括以行和列排列的多个存储器单元。该方法包括根据加载的数据位来从多个存储器单元中编程所选择的存储器单元。从编程的选定的存储单元中读取数据位。基于读取步骤的结果确定每个已编程的存储器单元是否已被成功编程。已经确定成功编程的存储器单元的编程被禁止。重复编程，读取，确定和禁止步骤，直到所选择的存储器单元被确定为已被成功编程。先前确定已被成功编程和禁止的存储器单元是不受限制的，并且随后在确定先前禁止的存储器单元不再被成功编程时重新编程。

9. 发明授权

US07230853B2 Selective erase method for flash memory 失效
标题翻译：闪存的选择性擦除方法
公开(公告)号：US07230853B2
公开(公告)日：2007-06-12
申请号：US10960542
申请日：2004-10-07
申请人： Wook-Hyun Kwon , Jung-In Han
发明人： Wook-Hyun Kwon , Jung-In Han
IPC分类号： G11C16/06
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/3468 , G11C16/3472 , G11C2216/18
摘要： Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.
摘要翻译：包括排列成行和列的一组存储器单元的闪速存储器件的选择性擦除方法包括对该组存储器单元执行擦除操作，并验证存储器单元组的擦除操作以确定存储器单元的阈值电压。识别包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元。对包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元的存储单元排除的存储器单元组执行进一步的擦除操作。

10. 发明申请

US20060018163A1 Selective erase method for flash memory 失效
标题翻译：闪存的选择性擦除方法
公开(公告)号：US20060018163A1
公开(公告)日：2006-01-26
申请号：US10960542
申请日：2004-10-07
申请人： Wook-Hyun Kwon , Jung-In Han
发明人： Wook-Hyun Kwon , Jung-In Han
IPC分类号： G11C16/04
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/3468 , G11C16/3472 , G11C2216/18
摘要： Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.
摘要翻译：包括排列成行和列的一组存储器单元的闪速存储器件的选择性擦除方法包括对该组存储器单元执行擦除操作，并验证存储器单元组的擦除操作以确定存储器单元的阈值电压。识别包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元。对包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元的存储单元排除的存储器单元组执行进一步的擦除操作。

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