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1. 发明授权

US06927482B1 Surface mount package and method for forming multi-chip microsensor device 失效
标题翻译：表面贴装封装及形成多芯片微传感器的方法
公开(公告)号：US06927482B1
公开(公告)日：2005-08-09
申请号：US10605472
申请日：2003-10-01
申请人： Woojin Kim , John Dancaster , John Logan , Aniela Bryzek
发明人： Woojin Kim , John Dancaster , John Logan , Aniela Bryzek
IPC分类号： B29C45/00 , B29C45/14 , B81B7/00 , G01L9/00 , G01L19/14 , H01L23/495
CPC分类号： B81C1/0023 , B29C45/0053 , B29C45/14655 , B81B2201/0264 , G01L19/0084 , G01L19/141 , G01L19/148 , H01L2224/48247 , H01L2224/49171 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012
摘要： A surface mount package for a multi-chip device has a leadframe formed with first and second die pads and leadouts from the respective die pads. An environmentally responsive sensor chip is secured to the first die pad and an environmentally isolated chip is secured to the second die pad. The chips are electrically coupled through the lead frame. A body formed with an over molded portion encases the isolated chip and an open molded portion formed with a recess receives the environmentally sensitive chip. An apertured cover is secured in the recess to form a protective covering over the sensor chip and for allowing communication of the sensor chip externally of the package.
摘要翻译：用于多芯片器件的表面贴装封装具有由相应管芯焊盘形成的第一和第二管芯焊盘和引出件的引线框架。环境敏感的传感器芯片被固定到第一管芯焊盘，并且环境隔离的芯片被固定到第二管芯焊盘。芯片通过引线框架电耦合。形成有过模制部分的主体包围隔离的芯片，并且形成有凹部的开放模制部分接收环境敏感的芯片。有孔盖被固定在凹槽中以在传感器芯片上形成保护覆盖物，并允许传感器芯片在封装外部通信。

2. 发明授权

US07157312B2 Surface mount package and method for forming multi-chip microsensor device 有权
标题翻译：表面贴装封装及形成多芯片微传感器的方法
公开(公告)号：US07157312B2
公开(公告)日：2007-01-02
申请号：US11052290
申请日：2005-02-08
申请人： Woojin Kim , John Dancaster , John Logan , Aniela Bryzek
发明人： Woojin Kim , John Dancaster , John Logan , Aniela Bryzek
IPC分类号： H01L23/495 , G01L7/08
CPC分类号： B81C1/0023 , B29C45/0053 , B29C45/14655 , B81B2201/0264 , G01L19/0084 , G01L19/141 , G01L19/148 , H01L2224/48247 , H01L2224/49171 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012
摘要： A surface mount package for a multi-chip device has a leadframe formed with first and second die pads and readouts from the respective die pads. An environmentally responsive sensor chip is secured to the first die pad and an environmentally isolated chip is secured to the second die pad. The chips are electrically coupled through the lead frame. A body formed with an over molded portion encases the isolated chip and an open molded portion formed with a recess receives the environmentally sensitive chip. An apertured cover is secured in the recess to form a protective covering over the sensor chip and for allowing communication of the sensor chip externally of the package.
摘要翻译：用于多芯片器件的表面贴装封装具有引线框架，该引线框架由第一和第二管芯焊盘形成，并且从各个管芯焊盘读出。环境敏感的传感器芯片被固定到第一管芯焊盘，并且环境隔离的芯片被固定到第二管芯焊盘。芯片通过引线框架电耦合。形成有过模制部分的主体包围隔离的芯片，并且形成有凹部的开放模制部分接收环境敏感的芯片。有孔盖被固定在凹槽中以在传感器芯片上形成保护覆盖物，并允许传感器芯片在封装外部通信。

3. 发明申请

US20050146000A1 Surface mount package and method for forming multi-chip microsensor device 有权
标题翻译：表面贴装封装及形成多芯片微传感器的方法
公开(公告)号：US20050146000A1
公开(公告)日：2005-07-07
申请号：US11052290
申请日：2005-02-08
申请人： Woojin Kim , John Dancaster , John Logan , Aniela Bryzek
发明人： Woojin Kim , John Dancaster , John Logan , Aniela Bryzek
IPC分类号： B29C45/00 , B29C45/14 , B81B7/00 , G01L9/00 , G01L19/14 , H01L23/495
CPC分类号： B81C1/0023 , B29C45/0053 , B29C45/14655 , B81B2201/0264 , G01L19/0084 , G01L19/141 , G01L19/148 , H01L2224/48247 , H01L2224/49171 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012
摘要： A surface mount package for a multi-chip device has a leadframe formed with first and second die pads and readouts from the respective die pads. An environmentally responsive sensor chip is secured to the first die pad and an environmentally isolated chip is secured to the second die pad. The chips are electrically coupled through the lead frame. A body formed with an over molded portion encases the isolated chip and an open molded portion formed with a recess receives the environmentally sensitive chip. An apertured cover is secured in the recess to form a protective covering over the sensor chip and for allowing communication of the sensor chip externally of the package.
摘要翻译：用于多芯片器件的表面贴装封装具有引线框架，该引线框架由第一和第二管芯焊盘形成，并且从各个管芯焊盘读出。环境敏感的传感器芯片被固定到第一管芯焊盘，并且环境隔离的芯片被固定到第二管芯焊盘。芯片通过引线框架电耦合。形成有过模制部分的主体包围隔离的芯片，并且形成有凹部的开放模制部分接收环境敏感的芯片。有孔盖被固定在凹槽中以在传感器芯片上形成保护覆盖物，并允许传感器芯片在封装外部通信。

4. 发明授权

US08264074B2 Device for use as dual-sided sensor package 有权
标题翻译：用作双面传感器封装的设备
公开(公告)号：US08264074B2
公开(公告)日：2012-09-11
申请号：US12879143
申请日：2010-09-10
申请人： Woojin Kim , Aniela Bryzek , John Dancaster , Dong-Suk Kim
发明人： Woojin Kim , Aniela Bryzek , John Dancaster , Dong-Suk Kim
IPC分类号： H01L23/535
CPC分类号： B60C23/0408 , G01D11/245 , G01L19/0084 , G01L19/141 , G01L19/147 , H01L2224/48091 , H01L2224/49171 , H01L2924/00014
摘要： A sensor package, and in one embodiment a sensor package for surface mount applications, that comprises a leadframe with an upper and lower surface for receiving a device thereon. Embodiments of the sensor package comprise a first device secured to the upper surface, and a second device secured to the lower surface so as to place connective pads from each of the first device and the second device proximate to one side of the leadframe. The sensor package further comprises a lead that is positioned in the sensor package in a manner that prevents electrical connection with circuitry that is external of the housing. The lead has an end proximate the side of the lead frame where the connective pads are positioned on the upper and lower surfaces. The end configured to receive connections, e.g., wirebonds, from the connective pads in a manner connecting the first device and the second device independent of any external connections of the sensor package.
摘要翻译：传感器封装，并且在一个实施例中用于表面贴装应用的传感器封装，其包括具有用于在其上接收器件的上表面和下表面的引线框架。传感器封装的实施例包括固定到上表面的第一器件和固定到下表面的第二器件，以便将连接焊盘从第一器件和第二器件中的每一个靠近引线框架的一侧放置。传感器封装还包括以防止与壳体外部的电路的电连接的方式定位在传感器封装中的引线。引线具有靠近引线框架侧面的端部，其中连接焊盘位于上表面和下表面上。该端被配置为以连接第一设备和第二设备的方式从连接焊盘接收连接，例如引线键，而与传感器封装的任何外部连接无关。

5. 发明授权

US09490298B2 Magnetic memory devices having a perpendicular magnetic tunnel junction 有权
标题翻译：具有垂直磁隧道结的磁存储器件
公开(公告)号：US09490298B2
公开(公告)日：2016-11-08
申请号：US14264049
申请日：2014-04-28
申请人： Woojin Kim , Ki Woong Kim , Woo Chang Lim
发明人： Woojin Kim , Ki Woong Kim , Woo Chang Lim
IPC分类号： H01L29/82 , H01L21/8239 , H01L27/105 , H01L27/22 , H01L43/08 , G11C11/16 , H01F10/32
CPC分类号： H01L27/222 , G11C11/161 , H01F10/3204 , H01F10/3254 , H01F10/3286 , H01L27/224 , H01L43/02 , H01L43/08 , H01L43/10
摘要： A magnetic memory device may include a free magnetic structure and a reference magnetic structure that are separated from each other by a tunnel barrier. The free magnetic structure may include an exchange-coupling layer, and first and second free layers that are separated from each other by the exchange-coupling layer. The first free layer may be provided between the second free layer and the tunnel barrier. A thickness of the first free layer may be greater than a first maximum anisotropy thickness, being the thickness at which the first free layer has maximum perpendicular anisotropy. A thickness of the second free layer may be smaller than a second maximum anisotropy thickness, being the thickness at which the second free layer has maximum perpendicular anisotropy. A magnetic tunnel junction having two free layers with different thicknesses can enable a magnetic memory device that has increased MR ratio and reduced switching current.
摘要翻译：磁存储器件可以包括通过隧道势垒彼此分离的自由磁结构和参考磁性结构。自由磁结构可以包括交换耦合层，以及通过交换耦合层彼此分离的第一和第二自由层。第一自由层可以设置在第二自由层和隧道势垒之间。第一自由层的厚度可以大于第一最大各向异性厚度，即第一自由层具有最大垂直各向异性的厚度。第二自由层的厚度可以小于第二最大各向异性厚度，即第二自由层具有最大垂直各向异性的厚度。具有两个具有不同厚度的自由层的磁性隧道结可实现具有增加的MR比和降低的开关电流的磁存储器件。

6. 发明授权

US09424904B2 Magnetic memory devices including oxide multiferroic material 有权
标题翻译：磁记忆装置包括氧化物多铁性材料
公开(公告)号：US09424904B2
公开(公告)日：2016-08-23
申请号：US14526489
申请日：2014-10-28
申请人： Kilho Lee , Sangyong Kim , Woojin Kim , KyungTae Nam
发明人： Kilho Lee , Sangyong Kim , Woojin Kim , KyungTae Nam
IPC分类号： G11C11/02 , G11C11/16 , G11C11/22
CPC分类号： G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/221
摘要： A magnetic memory device is provided. The magnetic memory device includes a plurality of variable resistance devices connected to a word line, and a plurality of bit lines, each of which provides an electrical pathway between a corresponding one of the variable resistance devices and a read and write circuit. Each of the variable resistance devices includes a free layer and a pinned layer spaced apart from each other and having a tunnel barrier interposed therebetween, an assistant layer spaced apart from the tunnel barrier and having the free layer interposed therebetween, and an exchange coupling layer arranged between the free layer and the assistant layer. The exchange coupling layer has an electric polarization, which results from its ferroelectric property, and having a direction that can be changed by a voltage applied to the corresponding one of the bit lines.
摘要翻译：提供磁存储器件。磁存储器件包括连接到字线的多个可变电阻器件和多个位线，每个位线提供相应的一个可变电阻器件与读写电路之间的电路径。每个可变电阻装置包括自由层和钉扎层，彼此间隔开并具有插入其间的隧道势垒，辅助层与隧道势垒间隔开并且具有插入其间的自由层，并且布置有交换耦合层在自由层和辅助层之间。交换耦合层具有由其铁电性质产生的电极化，并且具有可以通过施加到相应的一个位线的电压而改变的方向。

7. 发明授权

US09318695B2 Magnetic memory devices having a uniform perpendicular nonmagnetic rich antisotropy enhanced pattern 有权
公开(公告)号：US09318695B2
公开(公告)日：2016-04-19
申请号：US14614724
申请日：2015-02-05
申请人： Sechung Oh , Jangeun Lee , Woojin Kim , Heeju Shin
发明人： Sechung Oh , Jangeun Lee , Woojin Kim , Heeju Shin
IPC分类号： H01L43/02 , H01L27/22 , H01L43/08 , H01L43/12 , H01L43/10
CPC分类号： H01L43/02 , G11C11/161 , H01L27/222 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

8. 发明授权

US09048412B2 Magnetic memory devices including magnetic layers separated by tunnel barriers 有权
标题翻译：磁存储器件包括由隧道屏障隔开的磁性层
公开(公告)号：US09048412B2
公开(公告)日：2015-06-02
申请号：US14206053
申请日：2014-03-12
申请人： Sechung Oh , Jangeun Lee , Jeahyoung Lee , Woojin Kim , Woo Chang Lim , Junho Jeong , Sukhun Choi
发明人： Sechung Oh , Jangeun Lee , Jeahyoung Lee , Woojin Kim , Woo Chang Lim , Junho Jeong , Sukhun Choi
IPC分类号： H01L29/82 , H01L43/02 , B82Y25/00 , G11C11/16 , H01F10/32 , H01L43/08 , H01L43/10 , H01F10/12
CPC分类号： H01L43/02 , B82Y25/00 , G11C11/16 , G11C11/161 , H01F10/123 , H01F10/3236 , H01F10/3254 , H01F10/3268 , H01F10/3286 , H01L43/08 , H01L43/10
摘要： A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer.
摘要翻译：磁存储器件可以包括第一垂直磁性层，第一垂直磁性层上的非磁性层和非磁性层上的第一结磁性层，其中非磁性层位于第一垂直磁性层之间和第一结磁性层。隧道势垒可以在第一结磁性层上，其中第一结磁性层位于非磁性层和隧道势垒之间。第二结磁性层可以在隧道势垒上，其中隧道势垒在第一和第二结磁层之间，第二垂直磁性层可以在第二结磁性层上，第二结磁性层位于隧道势垒之间和第二垂直磁性层。

9. 发明申请

US20150115380A1 MAGNETIC MEMORY DEVICE 审中-公开
标题翻译：磁记忆装置
公开(公告)号：US20150115380A1
公开(公告)日：2015-04-30
申请号：US14583831
申请日：2014-12-29
申请人： Jangeun Lee , Sechung Oh , Jeahyoung Lee , Woojin Kim , Junho Jeong , Woo Chang Lim
发明人： Jangeun Lee , Sechung Oh , Jeahyoung Lee , Woojin Kim , Junho Jeong , Woo Chang Lim
IPC分类号： H01L43/10 , H01L43/02
CPC分类号： H01L43/10 , B82Y25/00 , G11C11/161 , H01F10/123 , H01F10/3254 , H01F10/3272 , H01F10/3286 , H01L27/222 , H01L43/02 , H01L43/08
摘要： A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the first vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer.
摘要翻译：提供磁存储器件。所述磁存储器件包括：衬底上的第一垂直磁性层和第二垂直磁性层，所述第一垂直磁性层和所述第二垂直磁性层之间的隧道势垒层，以及位于所述第一垂直磁性层之间的交换耦合层，第一垂直磁性层和第一垂直磁性层的第二子层。

10. 发明授权

US08987850B2 Magnetic memory devices having a uniform perpendicular nonmagnetic rich antisotropy enhanced pattern 有权
标题翻译：磁记忆体装置具有均匀的垂直非磁性富集反相增强图案
公开(公告)号：US08987850B2
公开(公告)日：2015-03-24
申请号：US14196666
申请日：2014-03-04
申请人： Sechung Oh , Jangeun Lee , Woojin Kim , Heeju Shin
发明人： Sechung Oh , Jangeun Lee , Woojin Kim , Heeju Shin
IPC分类号： H01L29/82 , H01L43/00 , H01L43/02 , H01L43/08 , H01L43/12
CPC分类号： H01L43/02 , G11C11/161 , H01L27/222 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.
摘要翻译：提供了磁存储器件，电子系统和包括其的存储卡，其制造方法以及控制磁性图案的磁化方向的方法。在磁存储器件中，不平行于自由图案的一个表面的原子磁矩在自由图案中增加。因此，可以减小磁存储器件的临界电流密度，使得磁存储器件的功耗被降低或最小化，和/或磁存储器件被改进或优化以达到更高的集成度。

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